RISC-V Instruction Set Extensions for Lightweight Symmetric Cryptography

Cheng, Hongbo; Großschädl, Johann; Marshall, Ben R.; Page, Daniel; Pham, Thinh

doi:10.46586/tches.v2023.i1.193-237

Cited by 7 publications

(3 citation statements)

References 15 publications

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“…Some analysis was made by El-hajj, M. et al to further investigate the adequate cryptographic algorithms for these systems by evaluating and benchmarking more than 39 symmetric block ciphers [16]. The work by Hao Cheng et al [17] provided the completed fundamental analysis, design, implementation results, hardware, and software of an ISE (instruction set extension) for 10 lightweight cryptography algorithms. In addition to utilizing the C programing language for pure software implementations [18], it seemed that the preferred implementation approach also involved using an ISE.…”

Section: Related Workmentioning

confidence: 99%

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

Pham

et al. 2023

Future Internet

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The security of Internet of Things (IoTs) devices in recent years has created interest in developing implementations of lightweight cryptographic algorithms for such systems. Additionally, open-source hardware and field-programable gate arrays (FPGAs) are gaining traction via newly developed tools, frameworks, and HDLs. This enables new methods of creating hardware and systems faster, more simply, and more efficiently. In this paper, the implementation of a system-on-chip (SoC) based on a 32-bit RISC-V processor with lightweight cryptographic accelerator cores in FPGA and an open-source integrating framework is presented. The system consists of a 32-bit VexRiscv processor, written in SpinalHDL, and lightweight cryptographic accelerator cores for the PRINCE block cipher, the PRESENT-80 block cipher, the ChaCha stream cipher, and the SHA3-512 hash function, written in Verilog HDL and optimized for low latency with fewer clock cycles. The primary aim of this work was to develop a customized SoC platform with a register-controlled bus suitable for integrating lightweight cryptographic cores to become compact embedded systems that require encryption functionalities. Additionally, custom firmware was developed to verify the functionality of the SoC with all integrated accelerator cores, and to evaluate the speed of cryptographic processing. The proposed system was successfully implemented in a Xilinx Nexys4 DDR FPGA development board. The resources of the system in the FPGA were low with 11,830 LUTs and 9552 FFs. The proposed system can be applicable to enhancing the security of Internet of Things systems.

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Section: Related Workmentioning

confidence: 99%

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

Pham

et al. 2023

Future Internet

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“…Alternatively, dedicated hardware, such as the AES functional unit [63], can be added to the datapath of the main core. The work presented in [73] analyzes the building blocks of the Lightweight Cryptography (LWC) finalists to find the most suitable acceleration granularity, e.g., their smallest hardware addition is for the Xoodyak parity plane manipulation (xorrol) with only a 1.155× increase in the area of the main core.…”

Section: A Conceptual Overviewmentioning

confidence: 99%

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors

Anders,

Andreu,

Becker

et al. 2023

2023 IEEE European Test Symposium (ETS)

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With the continued success of the open RISC-V architecture, practical deployment of RISC-V processors necessitates an in-depth consideration of their testability, safety and security aspects. This survey provides an overview of recent developments in this quickly-evolving field. We start with discussing the application of state-of-the-art functional and system-level test solutions to RISC-V processors. Then, we discuss the use of RISC-V processors for safety-related applications; to this end, we outline the essential techniques necessary to obtain safety both in the functional and in the timing domain and review recent processor designs with safety features. Finally, we survey the different aspects of security with respect to RISC-V implementations and discuss the relationship between cryptographic protocols and primitives on the one hand and the RISC-V processor architecture and hardware implementation on the other. We also comment on the role of a RISC-V processor for system security and its resilience against side-channel attacks.

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“…There are fields such as Internet of Things (IoT) [1], [2], cybersecurity [3], [4], domain-specific processor [5], [6], etc., where one works directly with assembly code on real hardware rather than with high-level languages [7].…”

Section: Introductionmentioning

confidence: 99%

CREATOR: An Educational Integrated Development Environment for RISC-V Programming

Camarmas-Alonso,

Garcia-Carballeira,

Calderon-Mateos

et al. 2024

IEEE Access

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This article introduces a new integrated development environment called CREATOR (didaCtic and geneRic assEmbly progrAmming simulaTOR) that provides an interactive platform for educational assembly programming. CREATOR is specially designed for the academic environment, so it is very intuitive to users who are encountering assembly for the first time. It makes the traditional theory classes interactive, engaging students' participation. Moreover, it is a multiplatform simulator that can be used with a web browser without requiring a server or additional installations, and it can be used on different types of devices. CREATOR allows all the necessary steps to be performed on the same tool, from the implementation of the assembly program to its execution on real hardware. For this purpose, it allows editing, compiling, simulating, debugging, and loading the program on the hardware device without auxiliary software. In addition, it is also capable of detecting compilation errors, execution errors, and violations of the parameter passing convention, helping users understand the reason for a given error so that they can resolve it. CREATOR offers the RISC-V and MIPS32 architectures by default. However, it is possible to modify these architectures or add new architectures in the tool as needed by any user. This feature allows teachers to prepare practical labs adapted to the teaching objectives, and it can also be used for research, e.g., for the study of different instruction sets. INDEX TERMSAssembly programming, educational simulator, ESP32-RISCV, integrated development environment (IDE), RISC-V.

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RISC-V Instruction Set Extensions for Lightweight Symmetric Cryptography

Cited by 7 publications

References 15 publications

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors

CREATOR: An Educational Integrated Development Environment for RISC-V Programming

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