RISC-V Graphics Rendering Instruction Set Extensions for Embedded AI Chips Implementation

Zhou, Yuzhi; Jin, Xi; Xiang, Tian

doi:10.1145/3378904.3378926

Cited by 5 publications

(3 citation statements)

References 8 publications

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“…However, RISC-V has no standard extensions for graphic computing. Recent works have designed Single Instruction Multiple-Thread (SIMT) execution [9], [57] and graphics rendering [45] instruction set extensions for efficient graphics computing.…”

Section: Graphic Computingmentioning

confidence: 99%

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RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions. Nowadays, RISC-V is a popular ISA for embedded processors. However, there is still a gap between the capabilities of RISC-V and the requirements of various emerging computing scenarios (e.g., artificial intelligence, cloud computing). Recently, the RISC-V standards organization has continuously introduced new ISA extensions to meet the needs of advanced computing. There are also a variety of novel research proposed customized extensions of RISC-V for certain scenarios. As far as we know, there is a lack of a survey to systematically present the research progress of RISC-V ISA extensions. The goal of this paper is to provide a comprehensive survey on existing works about RISC-V ISA extensions. First, the application scenarios of RISC-V are introduced, and the requirements for ISA extensions are analyzed. Then, we survey the progress of official RISC-V ISA extension specification and recent research on RISC-V ISA extension. Finally, we highlight some possible future research opportunities on the RISC-V ISA extension.INDEX TERMS RISC-V, instruction set architecture, extensions, survey.

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Section: Graphic Computingmentioning

confidence: 99%

“…In terms of software, they further modified the software stack to make Vortex support OpenCL and OpenGL. In addition to SIMT execution instruction set extension, Zhou et al [45] proposed a RISC-V graphics rendering instruction set extension, and designed the corresponding SoC. This SoC can be used in AI chips for graphic rendering.…”

Section: Graphic Computingmentioning

confidence: 99%

RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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“…Both ISAs provide productivity in the custom ISE definition process through the guidelines in the ISA documentation [17], [18]. Indeed, several studies applied the ASIP concept with one of these ISAs for systems targeting AI applications [19], [20], [21], [22]. However, most of those studies concentrate on applying this concept to complex AI algorithms such as deep learning and convolutional neural networks (CNN) [23], [24], [25], [26], [27], [28].…”

Section: Introductionmentioning

confidence: 99%

The Design of Optimized RISC Processor for Edge Artificial Intelligence Based on Custom Instruction Set Extension

Lee

2023

IEEE Access

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Edge computing is becoming increasingly popular in artificial intelligence (AI) application development due to the benefits of local execution. One widely used approach to overcome hardware limitations in edge computing is heterogeneous computing, which combines a general-purpose processor with a domain-specific AI processor. However, this approach can be inefficient due to the communication overhead resulting from the complex communication protocol. To avoid communication overhead, the concept of an application-specific instruction set processor based on customizable instruction set architecture (ISA) has emerged. By integrating the AI processor into the processor core, on-chip communication replaces the complex communication protocol. Further, custom instruction set extension (ISE) reduces the number of instructions needed to execute AI applications. In this paper, we propose a uniprocessor system architecture for lightweight AI systems. First, we define the custom ISE to integrate the AI processor and GPP into a single processor, minimizing communication overhead. Next, we designed the processor based on the integrated core architecture, including the base core and the AI core, and implemented the processor on an FPGA. Finally, we evaluated the proposed architecture through simulation and implementation of the processor. The results show that the designed processor consumed 6.62% more lookup tables and 74% fewer flip-flops while achieving up to 193.88 times enhanced throughput performance and 52.75 times the energy efficiency compared to the previous system.

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LLVM RISC-V RV32X Graphics Extension Support and Characteristics Analysis of Graphics Programs

Wang

2023

IEEE Access

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RISC-V Graphics Rendering Instruction Set Extensions for Embedded AI Chips Implementation

Cited by 5 publications

References 8 publications

RISC-V Instruction Set Architecture Extensions: A Survey

RISC-V Instruction Set Architecture Extensions: A Survey

The Design of Optimized RISC Processor for Edge Artificial Intelligence Based on Custom Instruction Set Extension

LLVM RISC-V RV32X Graphics Extension Support and Characteristics Analysis of Graphics Programs

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