RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs

Chen, Gengjie; Pui, Chak-Wa; Chow, Wing-Kai; Lam, Ka-Chun; Kuang, Jian; Young, Evangeline F. Y.; Yu, Bei

doi:10.1109/tcad.2017.2778058

Cited by 39 publications

(10 citation statements)

References 35 publications

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“…Since we attempt to locate the most congested region in the source code, the accuracy of our model is sufficient to solve our problem and guide the subsequent optimization in HLS. In physical design, routing congestion is modeled to guide the placement with high accuracy [5,6], because informative physical metrics can be obtained during the placement stage such as the number of bounding boxes, the net cuts per region and the pin count within a gcell. They require a highly accurate model to predict the routability, decide the location of each element and improve the quality of their placement algorithms.…”

Section: A Estimation Accuracymentioning

confidence: 99%

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Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

Zhao

Liang

Sinha

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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High-level synthesis (HLS) shortens the development time of hardware designs and enables faster design space exploration at a higher abstraction level. Optimization of complex applications in HLS is challenging due to the effects of implementation issues such as routing congestion. Routing congestion estimation is absent or inaccurate in existing HLS design methods and tools. Early and accurate congestion estimation is of great benefit to guide the optimization in HLS and improve the efficiency of implementation. However, routability, a serious concern in FPGA designs, has been difficult to evaluate in HLS without analyzing post-implementation details after Place and Route. To this end, we propose a novel method to predict routing congestion in HLS using machine learning and map the expected congested regions in the design to the relevant high-level source code. This is greatly beneficial in early identification of routability oriented bottlenecks in the high-level source code without running timeconsuming register-transfer level (RTL) implementation flow. Experiments demonstrate that our approach accurately estimates vertical and horizontal routing congestion with errors of 6.71% and 10.05% respectively. By presenting Face Detection application as a case study, we show that by discovering the bottlenecks in high-level source code, routing congestion can be easily and quickly resolved compared to the efforts involved in RTL level implementation and design feedback.

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Section: A Estimation Accuracymentioning

confidence: 99%

“…In physical design, many works [5]- [7] predict routing congestion to guide FPGA placement. With informative physical metrics, routing congestion can be predicted with high accuracy.…”

Section: Introductionmentioning

confidence: 99%

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

Zhao

Liang

Sinha

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…On the other hand, analytic placement techniques [9][10][11][12] achieve the placement goals through continuous and differential expressions. Analytic placers usually give good results in a short time, but they are often coupled with simulated annealing-based detailed placers for further refinement and improvement of the results [13]. Apart from being used for additional refinement, simulated annealing-based placers are also used stand-alone for placement in FPGA back-end flows [14].…”

Section: Introductionmentioning

confidence: 99%

Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning

Baig

Farooq

2022

Electronics

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Over the past few years, the computation capability of field-programmable gate arrays (FPGAs) has increased tremendously. This has led to the increase in the complexity of the designs implemented on FPGAs and to the time taken by the FPGA back-end flow. The FPGA back-end flow comprises of many steps, and routing is one of the most critical steps among them. Routing normally constitutes more than 50% of the total time taken by the back-end flow and an optimization at this step can lead to overall optimization of the back-end flow. In this work, we propose enhancements to the routing step by incorporating a reinforcement learning (RL)-based framework. In the proposed RL-based framework, we use the ϵ-greedy approach and customized reward functions to speed up the routing step while maintaining similar or better quality of results (QoR) as compared to the conventional negotiation-based congestion-driven routing solution. For experimentation, we use two sets of widely deployed, large heterogeneous benchmarks. Our results show that, for the RL-based framework, the ϵ-greedy greedy approach combined with a modified reward function gives better results as compared to purely greedy or exploratory approaches. Moreover, the incorporation of the proposed reward function in the RL-based framework and its comparison with a conventional routing algorithm shows that the proposed enhancement requires less routing time while giving similar or better QoR. On average, a speedup of 35% is recorded for the proposed routing enhancement as compared to negotiation-based congestion-driven routing solutions. Finally, the speedup of the routing step leads to an overall reduction in the execution time of the back-end flow of 25%.

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“…While these methods have high scalability, they typically need a detailed improvement stage to fully optimize an FPGA design. These detailed refinements are often performed using either low temperature simulated annealing or greedy block moves, as in GPlace3.0 [10] and RippleFPGA [11]. However, these methods do not take different characteristics of each circuit into the decision-making process and use the same static flow for different designs.…”

Section: Introductionmentioning

confidence: 99%

Guiding FPGA Detailed Placement via Reinforcement Learning

Esmaeili

Martin

Areibi

et al. 2022

2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)

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Field Programmable Gate Array (FPGA) placement is an important optimization step within the CAD implementation flow. Several metrics have to be optimized during placement including wirelength, congestion, timing, and most important routability. This thesis proposes to use Reinforcement Learning to further enhance the solution quality provided by the detailed placement stage. We show that a well-trained RL agent can capture different characteristics of each circuit placement and use these features in the decision-making process. The proposed RL framework targets simultaneously two objectives in the form of wirelength and external pin count to further improve circuit routability. Results obtained indicate the proposed RL-enhanced algorithm can reduce the runtime by 50% while achieving comparable solution quality to the GPlace3.0 detailed placement. These results can be further improved by refinement of the RLenhanced algorithm which motivates further exploration of integrating RL techniques in the FPGA CAD flow.iii ACKNOWLEDGEMENTS I would like to take this opportunity to express my sincere appreciation and thanks to my advisor Dr. Shawki Areibi and Dr. Gary Grewal for their constant support and guidance throughout my research and writing this thesis. I also would like to thank my colleagues in the ISLAB: Timothy Martin, Mohsen Fathi, and Roni Mittal. Their help and collaboration paved the way to make this work possible. Last but not least, I want to thank my family for being present in every stage of my life. Thank you for being so incredible. iv To my family whose love and encouragement helped accomplish this thesis.

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RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs

Cited by 39 publications

References 35 publications

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning

Guiding FPGA Detailed Placement via Reinforcement Learning

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