RF Performance and Modeling of Si/SiGe Resonant Interband Tunneling Diodes

Abstract

The RF performance of two different Si-based resonant interband tunneling diodes (RITD) grown by low-temperature molecular beam epitaxy (LT-MBE) were studied. An RITD with an active region of B -doping plane/2 nm i-Si 0 5 Ge 0 5 1 nm i-Si/P -doping plane yielded a peak-to-valley current ratio (PVCR) of 1.14, resistive cutoff frequency ( 0 ) of 5.6 GHz, and a speed index of 23.3 mV/ps after rapid thermal annealing at 650 C for 1 min. To the authors' knowledge, these are the highest reported values for any epitaxially grown Si-based tunnel diode. Another RITD design with an active region of 1 nm p+ Si 0 6 Ge 0 4 B -doping plane/4-nm i-Si 0 6 Ge 0 4 2 nm i-Si/P -doping plane and annealed at 825 C for 1 min had a PVCR of 2.9, an 0 of 0.4 GHz, and a speed index of 0.2 mV/ps. A small signal model was established to fit the measured 11 data for both device designs. Approaches to increase 0 are suggested based on the comparison between these two diodes. The two devices exhibit substantially different junction capacitance/bias relationships, which may suggest the confined states in the -doped quantum well are preserved after annealing at lower temperatures but are reduced at higher temperature annealing. A comprehensive dc/RF semi-physical model was developed and implemented in Agilent advanced design system (ADS) software. Instabilities in the negative differential resistance (NDR) region during dc measurements were then simulated.

Strain-Engineered Si/SiGe Resonant Interband Tunneling Diodes Grown on $\hbox{Si}_{0.8}\hbox{Ge}_{0.2}$ Virtual Substrates With Strained Si Cladding Layers

“…One advantage offered by SiGe virtual substrates is that a higher overall Ge content can be inserted in the spacer region to increase the tunneling probability, hence raising the resistive cutoff frequency, without exceeding the critical thickness [6]. This is partially promoted by barrier lowering and greater momentum mixing induced with the added Ge content due to the decreasing energy difference between the L and Γ valleys with the increasing Ge content.…”

90 nm 32 $\times$ 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation

“…The current source represents the nonlinear dc current of the RITD and is modeled using a polynomial fit to the measured dc I-V characteristics. A junction capacitance of 15.4 fF m has been obtained experimentally for a 6 nm spacer thickness RITD based upon a small signal model fit to measured S-parameters [18]. Assuming the capacitance is given simply by a parallel plate capacitor where is the tunneling spacer thickness, is the permittivity and A is the device area, the junction capacitance for an 8 nm spacer thickness would be 11.6 fF m approximately, normalized per unit area.…”

Accurately measuring current-voltage characteristics of tunnel diodes

“…Since tunnel diode has NDR, it potentially has the oscillation issue during measurement. Oscillations will distort the measured I-V characteris- tics, causing the measured I-V curves to have "plateau" and "double-humped" structures in the NDR region [2]- [4]. Thus, the I-V characteristics of such structures are usually not correct but are of pseudo I-V type.…”