RF packaging and passives: design, fabrication, measurement, and validation of package embedded inductors

Chickamenahalli, S.A.; Braunisch, Henning; Srinivasan, Suresh; He, Jiangqi; Shrivastava, U.A.; Sankman, Bob

doi:10.1109/tadvp.2005.850510

Cited by 19 publications

(4 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, as antennas and antenna tuners are designed to ensure that the VSWR does not change drastically between RX and TX bands to avoid excessive loss in the TX band or huge sensitivity degradation in the RX band, these simulations show that it is likely that this integrated tuner can maintain good isolation at both bands for different antennas. In case larger antenna impedance variations between the TX and RX frequencies are anticipated, a wider range of impedance can be achieved by employing higher in-package inductors [15], [16].…”

Section: Balance Network Designmentioning

confidence: 99%

Tunable CMOS Integrated Duplexer With Antenna Impedance Tracking and High Isolation in the Transmit and Receive Bands

Abdelhalem

Gudem

Larson

2014

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

A hybrid transformer-based integrated tunable duplexer is demonstrated. High isolation between the transmit and receive ports is achieved through electrical balance between the antenna and balance network impedances. A novel high-power-tolerant balance network, which can be tuned at both the transmit and receive frequencies, allows high isolation in both the transmit and receive bands even under realistic antenna impedance frequency dependence. To maintain high isolation despite antenna impedance variation, a feedback loop is employed to measure the transmitter leakage and correct the impedance of the balance network. An isolation 50 dB in the transmit and receive bands with an antenna voltage standing-wave ratio within 2:1 was achieved. The duplexer, along with a cascaded direct-conversion receiver, achieves a noise figure of 5.3 dB, a conversion gain of 45 dB, and consumes 51 mW of power. The insertion loss in the transmit path was less than 3.8 dB. Implemented in a 65-nm CMOS process, the chip occupies an active area of 2.2 mm .

show abstract

Section: Balance Network Designmentioning

confidence: 99%

Tunable CMOS Integrated Duplexer With Antenna Impedance Tracking and High Isolation in the Transmit and Receive Bands

Abdelhalem

Gudem

Larson

2014

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

show abstract

“…However, as the frequency increases, the magnetic field near the center of the wire increases the local reactance. The charge carriers then move towards the edge of the wire, decreasing the effective area and increasing the apparent resistance of the inductor winding [87], [88], capacitor [89], and resistor.…”

Section: G Componentsmentioning

confidence: 99%

Coupling for Power Line Communications: A Survey

Costa¹,

Queiroz²,

Adebisi³

et al. 2017

JCIS

View full text Add to dashboard Cite

The advent of power line communication (PLC) for smart grids, vehicular communications, internet of things and data network access has recently gained ample interest in industry and academia. Due to the characteristics of electric power grids and regulatory constraints, the effectiveness of coupling between the power line and PLC transceivers has become a very important issue. Coupling devices used to inject or extract data communication signals into or from power lines are very important components of a PLC system. There is, however, an obvious gap in the literature for a detailed review of existing PLC couplers. In this paper, we present a comprehensive review of couplers, which are required for narrowband and broadband PLC transceivers. Prevailing issues that protract the design of couplers and consequently subtended the inventions of different types of couplers are clearly described. We also provide a useful classification of PLC couplers based on the type of physical couplings, voltage levels, frequency bandwidth, propagation modes and a number of connections. This survey will guide researchers, as well as designers alike, into a quicker resourcing when studying coupling in narrowband and broadband PLC systems.

show abstract

“…According to a literature research, most related work focuses on electrical or thermal characterizations of selected on-package and chip-integrated components. With regard to electrical characterization, references [12], [18]- [20], for example, present measured impedance characteristics of on-package conventional and coupled inductors, without and with magnetic core, or examine parasitic resistances and capacitances of key components in Through Silicon Interposers, i.e., metal layers for BEOL interconnects, TSVs, redistribution layer, and micro-bumps. In case of thermal characterizations, related publications typically focus on the identification of peak chip temperatures in order to determine measures to prevent overheating, e.g., observations of chip temperatures under different load conditions [21], [22] and thermal characterization of a microprocessor to derive guidelines for on-line thermal management [23], [24].…”

Section: Introductionmentioning

confidence: 99%

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Bezerra

Krismer

Kolar

et al. 2020

IEEE Open J. Power Electron.

View full text Add to dashboard Cite

Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of 100 MHz and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCB-and inductorbased four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a 14 nm CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of 84.1 % at an output power of Pout = 640 mW and a switching frequency of fs = 50 MHz. The thermal measurements reveal that the maximum efficiency of the PMIC itself is between 88 % and 90 % at fs = 50 MHz and Pout ∈ [500 mW, 600 mW]; at Pout = 890 mW, a chip current density of 24.7 A/mm 2 is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs.

show abstract

RF packaging and passives: design, fabrication, measurement, and validation of package embedded inductors

Cited by 19 publications

References 17 publications

Tunable CMOS Integrated Duplexer With Antenna Impedance Tracking and High Isolation in the Transmit and Receive Bands

Tunable CMOS Integrated Duplexer With Antenna Impedance Tracking and High Isolation in the Transmit and Receive Bands

Coupling for Power Line Communications: A Survey

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Contact Info

Product

Resources

About