RF Noise of 65-nm MOSFETs in the Weak-to-Moderate-Inversion Region

Shi, Jinglin; Xiong, Yong Zhong; Kang, Kai; Nan, Lan; Lin, Fujiang

doi:10.1109/led.2008.2010464

Cited by 17 publications

(1 citation statement)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…6) that FoM LNA improves significantly with the gate length scaling for new design configuration. From Table 4, it can be concluded that improved FoM LNA owing to gate length scaling is primarily due to improvement in g m of the device [6] and lowering of NF [30].…”

Section: Figure-of-merit For Lnamentioning

confidence: 99%

Inter-modulation linearity investigation of an optimally designed and optimally biased LNA for wireless LAN

Singh

Alam

2015

Radioelectron.Commun.Syst.

View full text Add to dashboard Cite

This paper presents the effects of process parameters variations of new underlap SOI MOSFETs (underlap SOI technology with spacer covered) on linearity investigation of cascode low noise amplifier (LNA) for wireless LAN application. By quantifying the linearity of the LNA in-terms of third order intercept (IP3), the paper presents guidelines for optimum value of spacer s, film thickness T Si doping gradient d and gate length L G of the underlap device for linearity enhancement of the LNA. Based on a new Figure-of-Merit of LNA (FoM LNA ) involving available signal power gain G, IP3, noise figure (NF) and dc power consumption P dc , it has been found that FoM LNA in double gate (DG) configuration is much higher than single gate (SG) one at the optimum gate overdrive V OD = 75 mV. This is due to a combined effect of higher value of G and IP3 in the DG configuration. By comparing with limited available experimental data of 0.18 mm bulk technology, it has been found that using new underlap SOI MOSFETs with gate length of L G = 60 nm (effective gate length L eff = 92 nm) optimally designed and optimally biased LNA gives almost two times improvement in the proposed FoM LNA . With optimal bias the LNA achieved the following indicators: NF~2.27 dB, IP3~+7.75 dBm, G~20.86 dB and power consumption equal to 2.5 mW.

show abstract

Section: Figure-of-merit For Lnamentioning

confidence: 99%

Inter-modulation linearity investigation of an optimally designed and optimally biased LNA for wireless LAN

Singh

Alam

2015

Radioelectron.Commun.Syst.

View full text Add to dashboard Cite

show abstract

Modeling of high‐frequency noise of silicon CMOS transistors for RFIC design

Antonopoulos

Bucher

Papathanasiou

et al. 2014

Int J Numerical Modelling

View full text Add to dashboard Cite

SUMMARYThis work presents high-frequency noise measurements and compact modeling for a 90-nm silicon complementary metal-oxide-semiconductor (CMOS) technology in terms of radio frequency (RF) figures of merit (FoMs). Minimum noise figure (NF min ), equivalent noise resistance (R n ), optimum source reflection coefficient (Γ opt ), thermal noise excess factor and a recently introduced FoM for common-source low-noise amplifier (LNA) design are presented from a circuit design perspective. For this purpose, the behavior of the above mentioned RF FoMs is investigated over the level of channel inversion, providing insight from a circuit design point of view. The EKV3 MOSFET advanced compact model has been used in Spectre simulator, and results are validated over a large range of frequencies, channel lengths and bias points, for both N-type and P-type MOS devices. Optimum performance is shown to be shifted from higher to lower levels of inversion in moderate inversion, when scaling from 240 nm down to 100 nm. This is of great significance considering that the demand for low-power RF circuits becomes more and more imperative, as planar silicon CMOS technology is scaled to the deca-nanometer regime.

show abstract

Accurate RF modeling of nanoscale MOSFET using BSIM6 including low levels of inversion

Chalkiadaki¹,

Enz²

2014

Microelectronics Journal

View full text Add to dashboard Cite

RF Noise of 65-nm MOSFETs in the Weak-to-Moderate-Inversion Region

Cited by 17 publications

References 16 publications

Inter-modulation linearity investigation of an optimally designed and optimally biased LNA for wireless LAN

Inter-modulation linearity investigation of an optimally designed and optimally biased LNA for wireless LAN

Modeling of high‐frequency noise of silicon CMOS transistors for RFIC design

Accurate RF modeling of nanoscale MOSFET using BSIM6 including low levels of inversion

Contact Info

Product

Resources

About