RF-Noise Modeling in Advanced CMOS Technologies

Abstract

RF circuit design in deep-submicrometer CMOS technologies relies heavily on accurate modeling of thermal noise. Based on Nyquist's law, predictive modeling of thermal noise in MOSFETs was possible for a long time, provided that parasitic resistances and short-channel effects were properly accounted for. In sub-100-nm technologies, however, microscopic excess noise starts to play a significant role and its incorporation in thermal noise models is unavoidable. Here, we will review several crucial ingredients for accurate RF noise modeling, with emphasis on sub-100-nm technologies. In particular, a detailed derivation and discussion are presented of our microscopic excess noise model. It is shown to qualitatively explain the observed noise (across bias and geometry) in a wide range of commercially available sub-100-nm foundry processes. Besides, the impact of excess noise on the minimum noise figure is discussed.

On noise properties of transistors and amplifiers a critical review

“…Similar arguments can be made in reference to the so called "gate induced noise" which is to represent the noise imposed on the gate by channel carriers due to capacitve coupling (see for example the recent review papers on the modeling of noise in CMOS [14], [19], [20]). In a circuit model the postulated "gate induced noise" cannot be distinguished from the noise generated by the intrinsic gate resistance (see Fig.…”

“…The existence of thermal noise in the channel of a MOS field effect transistor was postulated in early work by Klassen and Prinz [13] and since has been wholeheartedly adopted by the CMOS community as the recent review paper clearly indicates [14]. The experimental data described in Section II does not indicate that the noise in CMOS should be treated any differently that in any other FET.…”

“…[t suffices to observe that the most recent invited paper [14] reviewing RF-noise modeling in advanced CMOS technologies does not even mention the general noise properties of the CMOS devices which, by virtue of the topologies of the noise equivalent networks used, must be satisfied. It also does not mention several papers which very successfully applied approach originated in [S] to the noise modeling of CMOS devices (for example [IS], [16], [17]).…”

“…In most of the channel carriers travel at saturated velocities and their average energy is quite high (they are "hot") [26]. Typically, the CMOS modeling approach deals with this fact by introducing the so called "excess drain noise" [14], even if the drain noise consists practically only of the "excess noise". Upon cooling any noise of thermal origin should be reduced in proportion to the ambient temperature.…”

A Small-Signal Analysis Based Thermal Noise Modeling Method for Rf Soi Mosfets

“…It is prerequisite for the application of modern SOI technologies in RF circuits to better understand noise mechanisms [2][3][4][5]. For the applications in low noise CMOS RF circuits such as low noise amplifier (LNA), accurate modeling of noise is quite important.…”