Review of wafer-level three-dimensional integration (3DI) using bumpless interconnects for tera-scale generation

Abstract

The prospects of three-dimensional (3D) integration for Terabyte large scale integration using bumpless interconnects with low-aspect-ratio TSVs and ultra-thinning are discussed. Bumpless (no bump) interconnects between wafers are a second-generation alternative to the use of microbumps for Wafer-on-Wafer (WOW) technology. Ultra-thinning of wafers down to 4 µm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of ThroughSilicon-Vias (TSVs). Our bumpless interconnects technology is classified into Via-Last, which is performed from the front side after thinning, and stacking Back-to-Front, in which any number of thinned 300 mm wafers and/or heterogeneous dies can be integrated. From an economic point of view, in many situations WOW is the leading 3D process because stacking at the wafer level drastically increases the processing throughput, and using multi-level bumpless interconnects, with individual wiring die-to-die, provides an appropriate yield that is equivalent to or greater than that achievable with 2D processes when scaling down to 22 nm nodes and beyond.

Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

“…As for the I/O power consumption, the first target of the bumpless HBM was one-thirtieth that of the current HBM2 [28], as shown in Figure 38. Figure 39 compares HBM2 with bumps [31][32][33] and bumpless HBM with respect to their data bandwidth and I/O buffer power, according as the number of I/O's [28,29,34,92,93]. Figure 39 compares HBM2 with bumps [31][32][33] and bumpless HBM with respect to their data bandwidth and I/O buffer power, according as the number of I/O's [28,29,34,92,93].…”

“…Figure 39 compares HBM2 with bumps [31][32][33] and bumpless HBM with respect to their data bandwidth and I/O buffer power, according as the number of I/O's [28,29,34,92,93]. Figure 39 compares HBM2 with bumps [31][32][33] and bumpless HBM with respect to their data bandwidth and I/O buffer power, according as the number of I/O's [28,29,34,92,93]. Bumpless HBM can achieve an ultra-high data bandwidth by increasing the I/O number to 1 K, 10 K and 100 K, and can lower the I/O buffer power to 1/2 or 1/4 by reducing the I/O pin frequency with a four-phase shielded I/O scheme, as illustrated in Figure 40.…”

“…Even in such small computers, high performance and large memory capacity are desired without sacrificing power efficiency and thermal dissipation. Conventional two-dimensional (2D) scaling and three-dimensional (3D) integration methods such as those used in High-Bandwidth-Memory (HBM) [30], however, will inevitably face an economic crisis due to the manufacturing costs and yield required [31][32][33].…”

Fundamental evaluation of orientation and grain size of Cu film in Cu/TaWN/SiO2/Si system

“…In Si-LSI (LSI) and 3D-LSI, significant miniaturization of the Cu interconnect has continued to progress, [1][2][3][4][5][6] where reduction of the interconnect resistance and improvement of the electromigration (EM) resistance are strongly required. 7) Under these circumstances, the realization of Cu(111) orientation, which is the most resistant to EM, is strongly desired.…”

XRD and EBSD analysis of Cu film on randomly oriented ZrN x film as the underlying materials

“…Copper films have low resistivity and excellent electromigration (EM) resistance, and they are the most commonly used interconnect material for silicon-large scale integration metallization and/or three-dimensional LSI such as throughsilicon-via technology. [1][2][3][4][5][6] However, because Cu films diffuse easily into SiO 2 and/or Si at low temperatures of less than 200 °C, 7,8) a diffusion barrier is required for reliable Cu interconnects. [9][10][11] Simultaneously, to further improve the EM resistance, an underlying material that can control the orientation and grain sizes of the Cu film is required.…”