Review of ferroelectric field‐effect transistors for three‐dimensional storage applications

Abstract

The ferroelectric field‐effect transistor (FeFET) is one of the leading contenders to succeed charge‐trap‐based flash memory (CTF) devices in the current vertically‐integrated NAND flash storage market. The operation of a FeFET is based on the field‐effect in the channel of the FET that is exerted by the uncompensated ferroelectric bound charge, which is also the fundamental source of the depolarization effect. This paper briefly reviews the current status of CTF‐based NAND flash memory as a benchmark for FeFET. Then, a one‐dimensional model based on a load‐line analysis of FeFET technology is presented. The paper subsequently deals with the two‐dimensional domain effect in nano‐sized NAND‐type FeFET devices. While NAND‐type FeFET operation is likely, current ferroelectric materials with high remanent polarization (Pr) of ∼10 μCcm‐2 and coercive field (Ec) of ∼1 MVcm‐1 are not feasible for use in such devices. This is fundamentally due to the high depolarization field induced by the unnecessarily high Pr, which not only destabilizes the memory state but also induces a severe interference effect between neighboring cells. Therefore, a new ferroelectric material with a moderately low Pr and higher Ec > ∼3 MVcm‐1 is necessary, along with structural innovation to minimize the interference effect.

Investigation of Optimum Deposition Conditions of Radio Frequency Reactive Magnetron Sputtering of Al0.7Sc0.3N Film with Thickness down to 20 nm

“…The necessary memory voltage window of FeFET for multiple‐ (quadruple or penta) level cells is ≈6–7 V, considering the contemporary NAND‐flash memory technology. [ 13 ] Since the theoretical memory voltage window of a FeFET is ≈2 V c , an E c of 6.5 MV cm −1 can produce the 2 V c of 6.5 V even for a 5 nm‐thick FE film if there are no adverse effects by the charge injection. [ 13 ] Such an adverse charge injection is mainly caused by the much higher polarization of the FE layer compared with the maximum semiconductor charge in Si (≈1 µC cm −2 ).…”

“…[ 13 ] Since the theoretical memory voltage window of a FeFET is ≈2 V c , an E c of 6.5 MV cm −1 can produce the 2 V c of 6.5 V even for a 5 nm‐thick FE film if there are no adverse effects by the charge injection. [ 13 ] Such an adverse charge injection is mainly caused by the much higher polarization of the FE layer compared with the maximum semiconductor charge in Si (≈1 µC cm −2 ). Therefore, it is still necessary to ensure that a much thinner AlScN film (<<10 nm) with a P r of <10 µC cm −2 could be achieved for it to be adopted as a feasible FE layer for next‐generation FeFET for high‐density information storage.…”

“…[ 10,11 ] The recent fluorite‐structured FE materials, such as (Hf,Zr)O 2 , have an E c of ≈1 MV cm −1 , but 2 V c of 10 nm‐thick (Hf,Zr)O 2 film is only ≈2 V. [ 6,12 ] Park et al. [ 13 ] recently reported that adverse charge injection due to the strong depolarization further decreases the memory window. Therefore, another complementary MOS‐compatible FE material with a higher E c is necessary for the next‐generation FeFET.…”

20‐3: Invited Paper: BEOL‐Compatible Ferroelectric Field‐Effect Transistors with Atomic Layer Deposition of Oxide Semiconductor Channel Toward Monolithic 3D Integration

“…Meanwhile, ALD provides the capability of conformal deposition of semiconductor channel on top of 3D structures. To fabricate both channel semiconductor and gate insulator by ALD enables tremendous new opportunities and flexibility for 3D device fabrication and integration, such as Fe-FET non-volatile memory with 3D NAND architecture (24,25).…”

Deep Insight into Steep‐Slope Threshold Switching with Record Selectivity (>4 × 1010) Controlled by Metal‐Ion Movement through Vacancy‐Induced‐Percolation Path: Quantum‐Level Control of Hybrid‐Filament

“…New mechanisms have been investigated to reduce the power and overcome the traditional limits of SS. Several emerging steep‐slope devices have been investigated recently, such as feedback field‐effect transistor (FET), [ 4 ] impact ionization FET (I‐MOS), [ 5 ] ferroelectric FET, [ 6 ] and tunnel FET (TFET). [ 7 ] However, these devices have disadvantages such as the large operation voltage and complex programming that limits the feedback device.…”