Review of candidate devices for neuromorphic applications

Lee, Jong-Ho; Noh, Yoohyun; Kim, Hyeong-Su; Kim, Jangsaeng; Bae, Jong-Ho; Woo, Sung Yun; Lee, Sung-Tae; Lim, Suhwan; Kang, Won-Mook; Seo, Young-Tak; Soo-Chang, Lee; Kwon, Dongseok; Oh, Seongbin

doi:10.1109/essderc.2019.8901694

Cited by 3 publications

(2 citation statements)

References 31 publications

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“…To achieve a ratio of VE and input voltage (Vinput) more than 99 %, the RS needs to be more than 1 MΩ when the number of rows or columns in the array is 64 or less as shown in Fig. 14. However, when the resistance in the RRAM devices is greater than 1 MΩ, the device variation becomes large [29]. Fig.…”

Section: Measured Characteristics Of the Nand Cells As Synaptic mentioning

confidence: 99%

NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density Quantized Neural Networks With Binary Neuron Activation of (1, 0)

et al. 2020

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We propose a novel synaptic architecture based on a NAND flash memory for highly robust and high-density quantized neural networks (QNN) with 4-bit weight and binary neuron activation, for the first time. The proposed synaptic architecture is fully compatible with the conventional NAND flash memory architecture by adopting a differential sensing scheme and a binary neuron activation of (1, 0). A binary neuron enables using a 1-bit sense amplifier, which significantly reduces the burden of peripheral circuits and power consumption and enables bitwise communication between the layers of neural networks. Operating NAND cells in the saturation region eliminates the effect of metal wire resistance and serial resistance of the NAND cells. With a read-verify-write (RVW) scheme, low-variance conductance distribution is demonstrated for 8 levels. Vector-matrix multiplication (VMM) of a 4-bit weight and binary activation can be accomplished by only one input pulse, eliminating the need of a multiplier and an additional logic operation. In addition, quantization training can minimize the degradation of the inference accuracy compared to post-training quantization. Finally, the low-variance conductance distribution of the NAND cells achieves a higher inference accuracy compared to that of resistive random access memory (RRAM) devices by 2~7 % and 0.04~0.23 % for CIFAR 10 and MNIST datasets, respectively. INDEX TERMS NAND flash, neuromorphic, synaptic device, hardware neural network, in-memory computing, quantized neural networks, deep neural network

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Section: Measured Characteristics Of the Nand Cells As Synaptic mentioning

confidence: 99%

NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density Quantized Neural Networks With Binary Neuron Activation of (1, 0)

et al. 2020

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“…These characteristics may not be suitable for edge computing in terms of power-efficiency and device endurance. In addition, many analog synaptic devices, including RRAM, show severe variation issues when operating with a small current density [6]. Thus, in order to build SNNs that are robust to variation, a synaptic device with a large current density should be used.…”

Section: Introductionmentioning

confidence: 99%

Spiking Neural Networks With Time-to-First-Spike Coding Using TFT-Type Synaptic Device Model

Soo-Chang

Woo

et al. 2021

IEEE Access

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In hardware-based spiking neural networks (SNNs), the conversion of analog input data into the arrival time of an input pulse is regarded as a good candidate for the encoding method due to its bioplausibility and power-efficiency. In this work, we trained an SNN encoded by time to first spike (TTFS) and performed an inference process using the behavior of the fabricated TFT-type flash synaptic device. The exponentially decaying synaptic current model required in the inference process was implemented by reading devices in the subthreshold region using triangle pulses. In a high-level system simulation, the TTFS-SNN (two-layer MLP with 512 hidden neurons) reached a high accuracy of 97.94%. Compared to conventional rate-encoded SNNs, TTFS-SNN made 2.9 times faster judgment and consumed ~10 times less energy in the inference process. Additionally, to use the network in a more stable condition, we propose a method to operate it using a rectangle pulse in the saturation region of the synaptic device. The distortion caused by this approximation was minimized by shortening the pulse width. As a result, the modified inference system showed an accuracy of 97.36%, and the prediction time and energy consumption were reduced 3.97-and 83.04-times when compared to those of the rate-SNN. Finally, we analyzed the sensitivity of the network performance due to unexpected issues that may occur in the hardware system and thus explained the competitiveness of the proposed synaptic behavior in the saturation region.

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Engineering current-voltage linearity in TFTs for analog and neuromorphic computing

Bestelink

Sagazan

Sporea

2021

2021 IEEE International Flexible Electronics Technology Conference (IFETC)

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Review of candidate devices for neuromorphic applications

Cited by 3 publications

References 31 publications

NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density Quantized Neural Networks With Binary Neuron Activation of (1, 0)

NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density Quantized Neural Networks With Binary Neuron Activation of (1, 0)

Spiking Neural Networks With Time-to-First-Spike Coding Using TFT-Type Synaptic Device Model

Engineering current-voltage linearity in TFTs for analog and neuromorphic computing

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