NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density Quantized Neural Networks With Binary Neuron Activation of (1, 0)

Abstract

We propose a novel synaptic architecture based on a NAND flash memory for highly robust and high-density quantized neural networks (QNN) with 4-bit weight and binary neuron activation, for the first time. The proposed synaptic architecture is fully compatible with the conventional NAND flash memory architecture by adopting a differential sensing scheme and a binary neuron activation of (1, 0). A binary neuron enables using a 1-bit sense amplifier, which significantly reduces the burden of peripheral circuits and power consumption and enables bitwise communication between the layers of neural networks. Operating NAND cells in the saturation region eliminates the effect of metal wire resistance and serial resistance of the NAND cells. With a read-verify-write (RVW) scheme, low-variance conductance distribution is demonstrated for 8 levels. Vector-matrix multiplication (VMM) of a 4-bit weight and binary activation can be accomplished by only one input pulse, eliminating the need of a multiplier and an additional logic operation. In addition, quantization training can minimize the degradation of the inference accuracy compared to post-training quantization. Finally, the low-variance conductance distribution of the NAND cells achieves a higher inference accuracy compared to that of resistive random access memory (RRAM) devices by 2~7 % and 0.04~0.23 % for CIFAR 10 and MNIST datasets, respectively. INDEX TERMS NAND flash, neuromorphic, synaptic device, hardware neural network, in-memory computing, quantized neural networks, deep neural network

Logic‐Compatible Charge‐Trapping Tunnel Field Effect Transistors for Low‐Power, High‐Accuracy, and Large‐Scale Neuromorphic Systems

“…Among the weight values, four fine-tuned weights (that is current levels) were selected to implement a quantized neural network (QNN), which is commonly utilized to evaluate the synaptic performance of various devices such as resistive RAM and flash devices. [21,22] Note that the ISPP scheme was used for fine-tuning operations rather than for on-chip learning operations. As shown in Figure 6, both CT-TFETs and CT-MOSFETs were trained to have four fine-tuned weights to implement the QNN.…”

The Opportunity of Negative Capacitance Behavior in Flash Memory for High‐Density and Energy‐Efficient In‐Memory Computing Applications

“…[1][2][3][4][5][6] In turn, flash memory is a promising candidate for use in synaptic devices. [7][8][9][10] The applicability of flash memory as a synapse has previously been demonstrated by utilizing its stable multistate operations, high on/off current ratio, exceptional retention characteristics, and the maturity of device technologies. However, like other electronic devices, [11][12][13][14] flash memory requires further research regarding is extremely challenging, given that FE domain formation and a corresponding multi-domain structure are highly feasible under most conditions.…”

“…device characteristics and array structures to realize IMC for artificial neural network inference, which involves repeating vectormatrix multiplication (VMM) operations at the edge. [8][9][10] As the charge tunneling mechanism of flash memory requires high-amplitude and long-duration voltage pulses, it currently requires a high operation voltage of ≈20 V and a low speed of ≈10 −3 s. [15] Additionally, incremental step pulse programming (ISPP) is a universal programming technique to achieve multilevel cell (MLC) flash memory with tight threshold voltage (V TH ) distributions. Ideally, the ISPP slope, which indicates program efficiency, linearly becomes unity.…”

Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

“…[1][2] While the transition from 2D to 3D structures has achieved a huge reduction in device size and bit cost, size scaling is still highly required for further development of 3D NAND flash memory. For instance, 3D charge-trap (CT) NAND flash memory, which usually adopts a macaroni-like vertical channel structure, has been rapidly developed because of its ultra-high storage density, low cost, well reliability, and diversity in novel applications [3][4][5][6][7][8]. The cylindrical shape of 3D CT NAND with ONO stack (SiO2/Si3N4/SiO2) from inside out is beneficial to the field distribution in the CT layer (Si3N4), which allows thicker tunneling oxide (SiO2) to enlarge the memory window.…”