Review and comparison of RSFQ asynchronous methodologies

Muller, Louis C.; Gerber, Hannah R.; Fourie, Coenrad J.

doi:10.1088/1742-6596/97/1/012109

Cited by 11 publications

(1 citation statement)

References 13 publications

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“…We set the targeted standard variation of this Gaussian distribution dataset under process variations based on the process control monitor data for 350-nm fabrication process SFQ5ee developed by MIT Lincoln Laboratory [30]. Then the parameters for global and local variations can be set according to the targeted standard variation [7,21,28].…”

Section: Variation Modelmentioning

confidence: 99%

A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits

Shahsavani

Zhou

et al. 2021

ACM Trans. Des. Autom. Electron. Syst.

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Single flux quantum (SFQ) logic is a promising technology to replace complementary metal-oxide-semiconductor logic for future exa-scale supercomputing but requires the development of reliable EDA tools that are tailored to the unique characteristics of SFQ circuits, including the need for active splitters to support fanout and clocked logic gates. This article is the first work to present a physical design methodology for inserting hold buffers in SFQ circuits. Our approach is variation-aware, uses common path pessimism removal and incremental placement to minimize the overhead of timing fixes, and can trade off layout area and timing yield. Compared to a previously proposed approach using fixed hold time margins, Monte Carlo simulations show that, averaging across 10 ISCAS’85 benchmark circuits, our proposed method can reduce the number of inserted hold buffers by 8.4% with a 6.2% improvement in timing yield and by 21.9% with a 1.7% improvement in timing yield.

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