Review and analysis of promising technologies with respect to Fifth generation networks

Kilaru, Seetaiah; K, Harikishore; Sravani, Tadepalli; L, Anvesh Chowdary; Balaji, T. S.

doi:10.1109/cnsc.2014.6906653

Cited by 13 publications

(5 citation statements)

References 9 publications

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“…AI and ML approaches have been widely used to solve complex problems within the upper layers of open system interconnection models, such as the deployment of wireless communication and cognitive radio relay networks, which produce significant performance improvements compared to secure wireless communication systems that were designed using conventional methods [133]. However, considering the recent success of current trends and the challenges of future wireless communication systems, such as high-speed connection demands in complex scenarios with unknown channel models, AI and ML approaches have now also been considered in the physical layer of wireless transmission strategies [134][135][136][137]. Recent advances in AI and ML techniques, especially deep learning (DL), reinforcement learning and convolutional neural networks (CNN), have provided novel concepts and potential opportunities to solve these complex problems.…”

Section: Overview Of Ai and ML Enabling Technologiesmentioning

confidence: 99%

A Review of Fundamental Optimization Approaches and the Role of AI Enabling Technologies in Physical Layer Security

Tefera

Jin

Zhang

2022

Sensors

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With the proliferation of 5G mobile networks within next-generation wireless communication, the design and optimization of 5G networks are progressing in the direction of improving the physical layer security (PLS) paradigm. This phenomenon is due to the fact that traditional methods for the network optimization of PLS fail to adapt new features, technologies, and resource management to diversified demand applications. To improve these methods, future 5G and beyond 5G (B5G) networks will need to rely on new enabling technologies. Therefore, approaches for PLS design and optimization that are based on artificial intelligence (AI) and machine learning (ML) have been corroborated to outperform traditional security technologies. This will allow future 5G networks to be more intelligent and robust in order to significantly improve the performance of system design over traditional security methods. With the objective of advancing future PLS research, this review paper presents an elaborate discussion on the design and optimization approaches of wireless PLS techniques. In particular, we focus on both signal processing and information-theoretic security approaches to investigate the optimization techniques and system designs of PLS strategies. The review begins with the fundamental concepts that are associated with PLS, including a discussion on conventional cryptographic techniques and wiretap channel models. We then move on to discuss the performance metrics and basic optimization schemes that are typically adopted in PLS design strategies. The research directions for secure system designs and optimization problems are then reviewed in terms of signal processing, resource allocation and node/antenna selection. Thereafter, the applications of AI and ML technologies in the optimization and design of PLS systems are discussed. In this context, the ML- and AI-based solutions that pertain to end-to-end physical layer joint optimization, secure resource allocation and signal processing methods are presented. We finally conclude with discussions on future trends and technical challenges that are related to the topics of PLS system design and the benefits of AI technologies.

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Section: Overview Of Ai and ML Enabling Technologiesmentioning

confidence: 99%

A Review of Fundamental Optimization Approaches and the Role of AI Enabling Technologies in Physical Layer Security

Tefera

Jin

Zhang

2022

Sensors

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“…In this paper for multiplication a systematic Vedic multiplier is using Urdhava Tiryagbhyam. this Vedic multiplier occupies less area and performs faster multiplication among the all multipliers [13][14][15][16][17][18][19][20][21]. By using conventional multiplier, it reduces the typical calculation which is difficult to compute the formula Urdhava Tiryagbhyam is applicable for all types of multiplications.…”

Section: Vedic Multipliermentioning

confidence: 99%

Low power and high speed GDI based convolution using Vedic multiplier

Priyanka¹,

Kumar²,

Priya³

et al. 2018

IJET

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Convolution is having extensive area of application in Digital Signal Processing. Convolution supports to evaluate the output of a system with arbitrary input, with information of impulse response of the system. Linear systems features are totally stated by the systems impulse response, as ruled by the mathematics of convolution. Primary necessity of any application to work fast is that rise in the speed of their basic building block. Multiplier, adder is said to be the important building blocks in the process of convolution. As these blocks consumes plentiful time to obtain the response of the system. Several methods are designed to progress the speed of the Multiplier and adder, among all GDI (Gate Diffusion Input) is under emphasis because of faster working and low power consumption. In this paper GDI based convolution is implemented using Vedic multiplier and adder in T-SPICE Software which increases the speed and consumes less power compared to CMOS technology.

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“…In this way, we get a total of 128 outputs from the comparison module each single output for 128 inputs. The distinct four inputs are combined to get a single output [14][15][16][17][18][19][20][21][22]. This procedure is tracked until we get our last 3 outputs.…”

Section: Architecturementioning

confidence: 99%

CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

Prasanna¹,

Sahiti²,

Raghuveera³

et al. 2018

IJET

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A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs.

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Review and analysis of promising technologies with respect to Fifth generation networks

Cited by 13 publications

References 9 publications

A Review of Fundamental Optimization Approaches and the Role of AI Enabling Technologies in Physical Layer Security

A Review of Fundamental Optimization Approaches and the Role of AI Enabling Technologies in Physical Layer Security

Low power and high speed GDI based convolution using Vedic multiplier

CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

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