In order to support ever increasing data rates and simultaneous numbers of users, high-order modulation schemes such as 1024-QAM and multipleinput multiple-output (MIMO) techniques are applied. Power amplifier (PA) power efficiency in MIMO systems benefits from beamforming array gain, but these MIMO systems require complex digital predistortion (DPD). It is shown that for some MIMO DPD algorithms and wide bandwidths, the overall DPD power consumption can exceed the overall PA power consumption already for transmitters (TXs) for scenarios with more than two antennas. In these scenarios, it can be beneficial for system power efficiency to employ more linear transmitter which do not need DPD, even when this comes at the cost of reduced PA power efficiency.Switched capacitor power amplifiers (SCPAs) are a class of digital transmitters which have shown promising results for high linearity with good drain efficiency (DE). Power efficiency of both the polar and two forms of quadrature implementations are investigated analytically, and in simulations. It is shown that for a given array capacitance and supply voltage, the polar architecture is the most power efficient. Compared to polar modulation, the switched capacitor (SC) loss for 64QAM is fundamentally 18% higher for quadrature modulation with a clock duty cycle of 50% (Q50) and 46% higher for quadrature modulation with a clock duty cycle of 25% (Q25) SCPAs, whereas the generated output powers are fundamentally 6 and 3dB lower, respectively. SCPA linearity is limited by AM-PM distortion, caused by a difference in output conductance in switching and non-switching driver cells. In a first chip, a driver cell implementation as an inverter with drain resistors is proposed which has equal output conductance in both cases, aiming to eliminate AM-PM distortion. This removes the need for DPD, along with the corresponding power consumption. An SCPA with these driver cells is implemented in a 22nm fully depleted silicon-on-insulator (FD-SOI) CMOS process, and demonstrates excellent DPD-less linearity with an adjacent channel leakage ratio (ACLR) of -50 dB and an error vector magnitude (EVM) of -45.5 dB for 5 MHz 1024 QAM signals at a DE of 8.8%. A matching network exploiting bondwires as high-Q inductors removes on-chip inductors and significantly reduces chip area.