Retiming gated-clocks and precharged circuit structures

Ishii, Alexander T.

doi:10.1109/iccad.1993.580073

Cited by 8 publications

(3 citation statements)

References 2 publications

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“…The OV 2 di erence constraints speci ed by Inequalities 3 and 8 can be computed in OV E + V 2 lg V steps by an all-pairs shortest-paths algorithm and can be solved in OV 3 steps by a Bellman-Ford algorithm for single-source shortest-paths. An asymptotically more e cient procedure that solves these constraints in OV E steps has been presented in 8 .…”

Section: Preliminariesmentioning

confidence: 99%

Asymptotically efficient retiming under setup and hold constraints

Papaefthymiou¹

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)

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In this paper we present a polynomial-time algorithm for retiming synchronous circuits with edge-triggered registers under setup and hold constraints. Given a circuit G and a target clock period c, our algorithm computes in OV 3 E steps a retimed circuit that achieves c and is free of hold violations, where V is the circuit's gate count, and E is the number of wires in the circuit. This is the rst polynomial-time algorithm ever reported for retiming with constraints on both long and short paths. The asymptotically e cient operation of our algorithm is based on a novel formulation of the timing constraints as an integer monotonic program with OE 2 inequalities.

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Section: Preliminariesmentioning

confidence: 99%

Asymptotically efficient retiming under setup and hold constraints

Papaefthymiou¹

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)

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“…Thus, a retiming approach should be able to move registers together with their load enables across logic blocks. This problem was addressed in [1] and [6]. Camposano and Plöger [1] stated several conditions for a valid retiming step involving load enable registers.…”

Section: Introductionmentioning

confidence: 99%

Retiming sequential circuits with multiple register classes

Eckl

Legl

1999

Proceedings of the Conference on Design, Automation and Test in Europe

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Retiming is an efficient technique for redistributing registers in synchronous circuits in order to improve the circuit performance. However, the traditional retiming approaches cannot handle circuits whose registers are controlled by different clock, reset, and load enable signals. We present basic theory and a comprehensive retiming approach for circuits with multiple clock, reset, and load enable signals. We retime these circuits having multiple register classes without explicitly modeling the reset or the load enable by additional logic. The presented concepts can be combined with a wide range of existing retiming approaches. Experimental results from retiming real designs for clock period minimization show the efficiency of the new approach.

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“…If the gated clock latches are marked as latches that caimot be moved, then the gated clock structure is preserved; however, optimality may be sacrificed. A better approach can be obtained by developing the techniques in [45].…”

Section: Some Of These Restrictions Arementioning

confidence: 99%

Fast algorithms for retiming large digital circuits

Maheshwari

Sapatnekar²

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Lee. Special thanks to Kaushik Gala for proofreading this thesis, and to Vara Varavithya for helping me with various formalities of thesis submmition. Thanks to Andrew, Jerry, Idarto, Chimai and other "sysadmin" people for keeping the computers up and running. I am grateful to National Science Foundation, Lucent Technologies and Design Automation Conference for fimding parts of my research; TKF.F. and Iowa State University for providing financial support to attend conferences; and IBM for providing me with the opportunity to work two summers. I feel indebted to my aunts, uncles and cousins in US for their love and emotional support and for many wonderful vacations; eind to my parents for having faith in me.

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Retiming gated-clocks and precharged circuit structures

Cited by 8 publications

References 2 publications

Asymptotically efficient retiming under setup and hold constraints

Asymptotically efficient retiming under setup and hold constraints

Retiming sequential circuits with multiple register classes

Fast algorithms for retiming large digital circuits

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