Rethinking split manufacturing: An information-theoretic approach with secure layout techniques

Abstract

Split manufacturing is a promising technique to defend against fab-based malicious activities such as IP piracy, overbuilding, and insertion of hardware Trojans. However, a network flow-based proximity attack, proposed by Wang et al. (DAC'16) [1], has demonstrated that most prior art on split manufacturing is highly vulnerable. Here in this work, we present two practical layout techniques towards secure split manufacturing: (i) gate-level graph coloring and (ii) clustering of same-type gates. Our approach shows promising results against the advanced proximity attack, lowering its success rate by 5.27x, 3.19x, and 1.73x on average compared to the unprotected layouts when splitting at metal layers M1, M2, and M3, respectively. Also, it largely outperforms previous defense efforts; we observe on average 8x higher resilience when compared to representative prior art. At the same time, extensive simulations on ISCAS'85 and MCNC benchmarks reveal that our techniques incur an acceptable layout overhead. Apart from this empirical study, we provide-for the first time-a theoretical framework for quantifying the layout-level resilience against any proximity-induced information leakage. Towards this end, we leverage the notion of mutual information and provide extensive results to validate our model.

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

“…Overall, while some BEOL wires can be correctly inferred, proximity attacks are limited, especially when split at lower layers. These findings are also confirmed by prior art [82], [85]- [88]. Finally, also note that only we as designers, having full access to the layout, can evaluate the attack, whereas any fab-based adversary can only run the attack for a "best guess."…”

Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

“…Therefore, an attacker requires further effort and know-how before he/she can obtain a complete netlist. In any case, attacks which can achieve 100% correctness when inferring all BEOL wires of industrial, largescale designs, possibly even with some placement-or routinglevel perturbations introduced for protection (e.g., see [39]- [42]), are yet to be demonstrated.…”

Protect Your Chip Design Intellectual Property

“…Various techniques have been proposed to safeguard FEOL layouts against proximity attacks, e.g., [77,[81][82][83][86][87][88][89][90][91]. They can be categorized into (i) placement-centric, (ii) routing-centric, and (iii) both placement-and routing-centric defenses.…”

“…Among others, Wang et al [82] and Sengupta et al [87] propose placement perturbation. Layout randomization is most secure, especially when splitting at the first metal layer, as shown by Sengupta et al [87]. However, this technique has limited scalability and significant layout cost for larger designs.…”