Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS

Luo, Ancheng; An, Fengwei; Zhang, Xiangyu; Chen, Lei; Mattausch, Hans Jürgen

doi:10.1109/tvlsi.2017.2774813

Cited by 3 publications

(8 citation statements)

References 33 publications

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“…Much less memory requirement is needed in this work when comparing to other FPGA schemes, due to the flexible regulation for memory allocation. A similarly small memory usage in our previous NNS-based architecture implemented in 65 nm CMOS [43], mainly results from the finite number of stored reference vectors. The memory usage in [43] will substantially increase with a larger number of onchip-stored reference vectors.…”

Section: Experimental Results and Analysis A Hardware Implementamentioning

confidence: 99%

“…A similarly small memory usage in our previous NNS-based architecture implemented in 65 nm CMOS [43], mainly results from the finite number of stored reference vectors. The memory usage in [43] will substantially increase with a larger number of onchip-stored reference vectors. In [39] twice the throughput (64fps) for HD resolution is obtained at the cost of consuming approximately twice memory, when compared to [38].…”

Section: Experimental Results and Analysis A Hardware Implementamentioning

confidence: 99%

“…Our previous works [42], [43] focused on a cell-based hardware architecture combined with NNS classification without feature normalization, simplifying the calculation and leading to a resolution flexibility for the video frame of up to 1024 ×∞ pixels. Approximately 31 fps in XGA (1024×768) throughput has been obtained when operating at 200 MHz, while consuming only 1.29 nJ/pixel of energy and 0.203 Mbit of on-chip memory.…”

Section: B Related Workmentioning

confidence: 99%

“…Theory and algorithm of the linear support vector machine (SVM) model were originally established by Vapnik [45]. Such a linear support vector machine (SVM) classifier is applied as it can produce higher recognition accuracy when compared to other classifiers including the NNS classifier applied in our previous works [42], [43]. For classification problems, the linear SVM approach in the feature space aims at constructing a classifier using a mathematical notation of the form:…”

Section: B Support Vector Machines Classifiermentioning

confidence: 99%

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A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier

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Significantly improved performance of the various learning algorithms has revived the interest in computer vision for recognition applications during the current decade. This paper reports a vision-based hardware recognition architecture combining the Haar-like feature extraction with the support vector machine (SVM) classification. To support an optimal tradeoff between resource requirements, processing speed, and recognition accuracy, a 12-bit fixed-point computation for block-based feature normalization and a recycling allocation of minimalized memory resources are proposed in this paper. Furthermore, an efficient scale generation of target objects for recognition is enabled by configurable windows with high size flexibility. Additionally, a parallel-partial SVM-classification architecture is developed for improving the recognition speed, by accumulating the partially completed SVM results for multiple windows in parallel. The proposed hardware architecture is verified with an Altera DE4 platform to achieve a high throughput rate of 216 and 70 f/s for XGA (1024×768) and HD (1920×1080) video resolutions, respectively. A recycled memory space of only 193 KB is sufficient for processing high-resolution images up to 2048×2048 pixels during online testing. Using the INRIA person dataset, 89.81% average precision and maximum accuracy of 96.93% for pedestrian recognition are realized. Furthermore, about 99.08% accuracy is achieved for two car recognition tasks using the UIUC dataset (side view of cars) and a frontal car dataset collected by ourselves at Hiroshima University with the proposed hardware-architecture framework.

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Section: Experimental Results and Analysis A Hardware Implementamentioning

confidence: 99%

Section: Experimental Results and Analysis A Hardware Implementamentioning

confidence: 99%

Section: B Related Workmentioning

confidence: 99%

Section: B Support Vector Machines Classifiermentioning

confidence: 99%

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A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier

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IEEE Access

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“…5) is used to analyze the neighborhood feature of the solder joints pixels. 18 Then, the extraction precision of regional solder joints can be improved using the following proposed extraction optimized algorithm based on (geometrical) neighborhood feature.…”

Section: Analysis Of Neighborhood Feature Of the Solder Joint Pixelsmentioning

confidence: 99%

A Novel Multi-Pattern Solder Joint Simultaneous Segmentation Algorithm for PCB Selective Packaging Systems

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Int. J. Patt. Recogn. Artif. Intell.

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To prevent any negative electromagnetic influence of high-density integrated circuits, an insulation package needs to be specially designed to shield it. Aiming at the low efficiency and material waste in traditional packaging methods, a printed circuit board (PCB) selective packaging system based on a multi-pattern solder joint simultaneous segmentation algorithm and three-dimensional printing technology is introduced in this paper. Firstly, the structure of PCB selective packaging system is designed. Secondly, to solve the existing problems, such as multi-pattern solder joints which are located densely in small welding areas and are hard to be extracted in the small-area integrated circuit board, a multi-pattern solder joint simultaneous segmentation algorithm is developed based on (geometrical) neighborhood features to extract and locate the optimal PCB solder joint areas. Finally, tests using three actual PCB are carried out to compare the proposed method with traditional multi-threshold solder joint extraction methods. Test results indicate that the proposed algorithm is simple and effective. Diverse solder joints can be optimally located and simultaneously extracted from the collected PCB image, which greatly improves the filling rate of the solder joint areas and filters out false pixels. Thus, this method provides a reliable location-finding tool to help place solder points in PCB selective packaging systems.

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Secure Cloud-Aided Object Recognition on Hyperspectral Remote Sensing Images

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Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS

Cited by 3 publications

References 33 publications

A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier

A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier

A Novel Multi-Pattern Solder Joint Simultaneous Segmentation Algorithm for PCB Selective Packaging Systems

Secure Cloud-Aided Object Recognition on Hyperspectral Remote Sensing Images

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