Resolving Endurance and Program Time Trade-Off of 40nm TaOx-Based ReRAM by Co-Optimizing Verify Cycles, Reset Voltage and ECC Strength

Hayakawa, Atsuna; Maeda, Kazuki; Fukuyama, Seiji; Takishita, Hirofumi; Yasuhara, Ryo; Mishima, Satoshi; Takeuchi, Ken

doi:10.1109/imw.2017.7939101

Cited by 12 publications

(6 citation statements)

References 3 publications

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“…After 10 4 set/reset cycles, the total BER increases. 30) Table I shows fluctuations of the tail bits among all measured cells. Over 10 5 set/reset cycles, the tail bits occur and increase.…”

Section: Experimental Methods and Characteristicsmentioning

confidence: 99%

85% endurance error reduction and data-retention lifetime enhancement by changing the reset voltage in 40 nm TaO _X -based ReRAM

Kinoshita

Yonai

Takeuchi

2020

Jpn. J. Appl. Phys.

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This paper proposes a changing reset voltage technique for 40 nm TaOX-based resistive random access memories (ReRAM). In the proposed technique, reset voltage (VRESET) changes at high endurance such as 104 set/reset cycles. The changing reset voltage technique decreases the measured total bit-error rate (BER) of both the low resistance state (LRS) and high resistance state (HRS) by 85%, compared with conventional fixed reset voltage. In addition, the current difference between LRS and HRS at probability = 50% (window) increases by 57% with the proposed technique, which increases the read margin between set and reset. Moreover, by decreasing the tail bits and expanding the read margin, the data-retention lifetime is increased. As a result, the changing reset voltage technique is recommended for high endurance and long data retention lifetime. Finally, this paper proposes a physical model of the proposed technique.

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Section: Experimental Methods and Characteristicsmentioning

confidence: 99%

85% endurance error reduction and data-retention lifetime enhancement by changing the reset voltage in 40 nm TaO _X -based ReRAM

Kinoshita

Yonai

Takeuchi

2020

Jpn. J. Appl. Phys.

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“…The conductance distribution expands as the number of Set/Reset cycles increases due to the expansion of the conductive filament and decrease in oxygen vacancy density. 32) If the cell current exceeds I ref against the desired resistance state, bit inversion occurs. Figure 9(c) shows the details of bit inversion.…”

Section: Nvm Device Non-ideality In Cimmentioning

confidence: 99%

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Higuchi¹,

Kobayashi²,

Misawa³

et al. 2023

Jpn. J. Appl. Phys.

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This paper proposes tiny and error tolerant Convolutional LSTM (ConvLSTM) for event-based vision sensor (EVS) data processing with Computation-in-Memory (CiM) that utilizes ReRAM. To handle the event data by ConvLSTM, the type and parameter of event representation are optimized to pre-process event data. To realize tiny and error tolerant ConvLSTM CiM, reduction of the bit precision and error tolerance in each ConvLSTM layer and weight are considered. On the other hand, reducing the bit precision degrades inference accuracy and error tolerance. ReRAM has non-idealities such as conductance variation and worn out by Set/Reset cycles that induces bit inversion. Thus, bit error rate at each Set/Reset cycles are investigated, and the bit precision of the weight is optimized to accept bit error rate of 0.1% in simulation. The proposed tiny ConvLSTM can reduce the size of memory by 91% compared with non-optimized ConvLSTM of that weight is represented in 32-bit precision.

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“…2. A large forming time variability is observed in all MIM stacks: in order to reduce the power consumption during Forming, the use of a program and verify will be beneficial [15]. When comparing stacks with same materials but different thickness such as A with B or C with D, we can observe that a thickness reduction of the insulator material generally causes a variability, forming cumulative time and energy (calculated as the product between forming voltage,current and time) reduction, resulting in an increase of both η and β fitting parameters.…”

Section: A Forming Operationmentioning

confidence: 99%

“…Even if this was already demonstrated in [14] for standard HfO 2 OxRRAM, this analysis allows to extend the validity of the relationship to MIM stacks featuring different materials and thicknesses. In conclusion, the choice of the insulator material will impact the time and power consumption during Forming, Set and Reset but not the cell-to-cell variability, which can be limited only at circuit and system level by using program with verify algorithms and ECC [15].…”

Section: B Set/reset Operationsmentioning

confidence: 99%

Cell-to-Cell Fundamental Variability Limits Investigation in OxRRAM Arrays

Grossi

Zambelli

Olivo

et al. 2018

IEEE Electron Device Lett.

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In this paper the fundamental variability limits of filament based OxRRAM are investigated considering different transistor sizes and MIM stacks featuring different materials and thicknesses. Cell-to-cell variability is analyzed through an extensive characterization of Forming, Set and Reset operations on 4kbits OxRRAM arrays. The results obtained in terms of switching voltage variability and resistance variability from cell to cell are compared and discussed to identify the variability limiting component as a function of the conduction regime and to understand the impact of transistor MIM stack parameters on variability and performances.

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Resolving Endurance and Program Time Trade-Off of 40nm TaOx-Based ReRAM by Co-Optimizing Verify Cycles, Reset Voltage and ECC Strength

Cited by 12 publications

References 3 publications

85% endurance error reduction and data-retention lifetime enhancement by changing the reset voltage in 40 nm TaO _X -based ReRAM

85% endurance error reduction and data-retention lifetime enhancement by changing the reset voltage in 40 nm TaO _X -based ReRAM

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Cell-to-Cell Fundamental Variability Limits Investigation in OxRRAM Arrays

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Resolving Endurance and Program Time Trade-Off of 40nm TaOx-Based ReRAM by Co-Optimizing Verify Cycles, Reset Voltage and ECC Strength

Cited by 12 publications

References 3 publications

85% endurance error reduction and data-retention lifetime enhancement by changing the reset voltage in 40 nm TaO X -based ReRAM

85% endurance error reduction and data-retention lifetime enhancement by changing the reset voltage in 40 nm TaO X -based ReRAM

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Cell-to-Cell Fundamental Variability Limits Investigation in OxRRAM Arrays

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85% endurance error reduction and data-retention lifetime enhancement by changing the reset voltage in 40 nm TaO _X -based ReRAM

85% endurance error reduction and data-retention lifetime enhancement by changing the reset voltage in 40 nm TaO _X -based ReRAM