Cell-to-Cell Fundamental Variability Limits Investigation in OxRRAM Arrays

Grossi, Alessandro; Zambelli, Cristian; Olivo, P.; Nowak, E.; Molas, G.; Nodin, J. F.; Perniola, L.

doi:10.1109/led.2017.2774604

Cited by 10 publications

(6 citation statements)

References 21 publications

(26 reference statements)

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“…As previously mentioned, filamentary, memristive VCM cells can be manufactured using different materials, being classified according to their switching mode, conductive path and switching mechanism. Different implementations of a HfO2-based memristor (TiN/HfO2/TiN or TiN/HfO2/Ti/ TiN) are described in [10,11,4,23] and a TaOx based memristor (Ta2O5/TaOx) proposed by Panasonic is described in [15,19,15]. The manufacturing process of memristive devices aims to create devices composed of three main parts, the Bottom Electrode (BE), the Transition Metal Oxide (TMO) and finally, the Top Electrode (TE).…”

Section: Manufacturing Process and Possible Defectsmentioning

confidence: 99%

“…A slightly different device form is the pillar cell, where the MIM layer stack is deposited as a whole and is finally etched into the desired shape. The BE and TE are contacted by vias [11]. Note that in this paper, the focus is laid on the crossbar cell design due to the possibility to build on every substrate, either a passive, planar disc or a CMOS-type substrate with contact pads reaching to the top surface [10].…”

Section: Manufacturing Process and Possible Defectsmentioning

confidence: 99%

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Review of Manufacturing Process Defects and Their Effects on Memristive Devices

et al. 2021

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Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down over the last forty years making possible the design of high-performance applications, following the predictions made by Gordon Moore and Robert H. Dennard in the 1970s. However, there is a growing concern that device scaling, while maintaining cost-effective production, will become infeasible below a certain feature size. In parallel, emerging applications including Internet-of-Things (IoT) and big data applications present high demands in terms of storage and computing capability, combined with challenging constraints in terms of size, power consumption and response latency. In this scenario, memristive devices have become promising candidates to complement the CMOS technology due to their CMOS manufacturing process compatibility, great scalability and high density, zero standby power consumption and their capacity to implement high density memories as well as new computing paradigms. Despite these advantages, memristive devices are also susceptible to manufacturing defects that may cause unique faulty behaviors that are not seen in CMOS, increasing significantly the complexity of test procedures. This paper provides a review about the manufacturing process of memristives devices, focusing on Valence Change Mechanism (VCM)-based memristive devices, and a comparative analysis of the CMOS and memristive device manufacturing processes. Moreover, this paper identifies possible manufacturing failure mechanisms that may affect these novel devices, completing the list of the already known mechanisms, and provides a discussion about possible faulty behaviors. Note that the identification of these mechanisms provides insights regarding the possible memristive devices’ defective behaviors, enabling to derive more accurate fault models and consequently, more suitable test procedures.

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Section: Manufacturing Process and Possible Defectsmentioning

confidence: 99%

Section: Manufacturing Process and Possible Defectsmentioning

confidence: 99%

Review of Manufacturing Process Defects and Their Effects on Memristive Devices

et al. 2021

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“…More precisely, it was showed that for median resistances higher than the dispersion follows a lognormal distribution with median parameter T50=172kΩ and form factor =0.78. is the quantum conductance unit corresponding to the creation of a single conductive nanowire (28). Consequently, large compliance currents induce higher variability and lower  even at the first Set/Reset operation, making challenging the development of RRAM technology for low power applications.…”

Section: Window Margin Variabilitymentioning

confidence: 99%

“…Where R is the cell resistance,  the barrier height and α related to the width of the barrier, assuming a parabolic longitudinal potential. Those parameters refer to the QPC model (28). Resistance standard deviation fundamental limit is linked to the discreteness of the number of elements (vacancies/ atoms) participating to the conduction, and following a Poisson distribution.…”

Section: Window Margin Variabilitymentioning

confidence: 99%

(Invited) Resistive Memories (RRAM) Variability: Challenges and Solutions

et al. 2018

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In this work, we address Resistive RAM (RRAM) variability. To this aim, we investigate various RRAM technologies (Oxide RAM and Conductive Bridging RAM), integrated on kb 1T1R arrays. Impact of variability is evaluated and discussed for various RRAM features: window margin, switching speed, consumption, retention and endurance. Solutions are proposed in order to improve overall RRAM performances. Optimized programming schemes are discussed. Importance of controlling the memory operation and programming energy to improve RRAM reliability is put in evidence.

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“…Therefore, considering and improving the reliability of designs for CIM are crucial. For the VCM-ReRAM devices, cycle-to-cycle (C2C) and device-to-device (D2D) switching variabilites as well as read instabilities [5][6][7] might occur which can lead to a variation in the observed device resistance or in the switching process. This possibly degrades the device performance as data storage cell or in CIM computation.…”

Section: Introductionmentioning

confidence: 99%

Improved Arithmetic Performance by Combining Stateful and Non‐Stateful Logic in Resistive Random Access Memory 1T–1R Crossbars

Brackmann,

Ziegler,

Jafari

et al. 2023

Advanced Intelligent Systems

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Computing‐in‐memory (CIM) is a promising approach for overcoming the memory‐wall problem in conventional von‐Neumann architectures. This is done by performing certain computation tasks directly in the storage subsystem without transferring data between storage and processing units. Stateful and non‐stateful CIM concepts are recently attracting lots of interest, which are demonstrated as logical complete, energy efficient, and compatible with dense crossbar structures. However, sneak‐path currents in passive resistive random access memory (RRAM) crossbars degrade the operation reliability and require the usage of active 1 Transistor–1 Resistance (1T‐1R) bitcell designs. In this article, the arithmetic performance and reliability are investigated based on experimental measurements and variability‐aware circuit simulations. Herein, it is aimed for the evaluation of logic operations specifically with fully integrated 1T–1R crossbar devices. Based on these operations, an N‐bit full adder with optimized energy consumption and latency is demonstrated by combining stateful and non‐stateful CIM logic styles with regard to the specific conditions in active 1T–1R RRAM crossbars.

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Cell-to-Cell Fundamental Variability Limits Investigation in OxRRAM Arrays

Cited by 10 publications

References 21 publications

Review of Manufacturing Process Defects and Their Effects on Memristive Devices

Review of Manufacturing Process Defects and Their Effects on Memristive Devices

(Invited) Resistive Memories (RRAM) Variability: Challenges and Solutions

Improved Arithmetic Performance by Combining Stateful and Non‐Stateful Logic in Resistive Random Access Memory 1T–1R Crossbars

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