Resolution-Selective and Resolution-Adaptive 2 to 8-Bit Flash ADC for High-Speed Application-Independent IC (HS-AIIC)

Abstract

Application-Specific ICs (ASIC) are manufactured in bulk for a long time. In this paper, an approach to High-Speed Application-Independent IC (HS-AIIC) design is discussed. A resolution-selective (RS) and resolution-adaptive (RA) 8-bit Flash ADC are designed for use in various high-speed applications. With the choice of resolution, one can work with the trade-off between speed, power consumption, and resolution for a particular application. The proposed resolution selection algorithm can be implemented for any set of resolutions for a flash ADC design. Further, an adaptive block is added to make the ADC design adaptive in nature so that we do not have to select a particular resolution manually. The proposed design entrusts on saving manufacturing cost and increases the functionality of ADC on a single chip. Proposed resolution adaptive 8-bit flash ADC design dissipates 512[Formula: see text]mW of power with an ENOB of 7.56 bits and SNDR of 46.27[Formula: see text]dB for 1[Formula: see text]GHz sampling clock pulse.