Resolution of dynamic memory allocation and pointers for the behavioral synthesis from C

Semeria, L.; Sato, K.; Micheli, G. De

doi:10.1109/date.2000.840289

Cited by 13 publications

(13 citation statements)

References 10 publications

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“…Hardware synthesis of programs written in a functional language is easier if the language is restricted, especially if closures are forbidden [4]. Indeed, closures require dynamic memory allocation in the general case, something which is trivial in a software environment but requires a heavy machinery with hardware [15].…”

Section: Rvc-cal Languagementioning

confidence: 99%

Software Code Generation for the RVC-CAL Language

Wipliez

Roquier

Nezan

2009

J Sign Process Syst

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The MPEG Reconfigurable Video Coding (RVC) framework is a new standard under development by MPEG that aims at providing a unified high-level specification of current and future MPEG video coding technologies using dataflow models. In this framework, a decoder is built as a configuration of video coding modules taken from the standard MPEG toolbox library or proprietary libraries. The elements of the library are specified by a textual description that expresses the I/O behavior of each module and by a reference software written using a subset of the CAL Actor Language named RVC-CAL. A decoder configuration is written in an XML dialect by connecting a set of CAL modules. Code generators are fundamental supports that enable the direct transformation of a high level specification to efficient hardware and software implementations. This paper presents a synthesis tool that from a CAL dataflow program generates C code and an associated SystemC model. The generated code is validated against the original CAL description simulated using the Open Dataflow environment. Experimental results of the translation of two descriptions of an MPEG-4 Simple Profile decoder with different granularities are shown and discussed.

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Section: Rvc-cal Languagementioning

confidence: 99%

Software Code Generation for the RVC-CAL Language

Wipliez

Roquier

Nezan

2009

J Sign Process Syst

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“…However, in embedded systems, where the entire application is usually visible to the compiler, an aggressive compiler can perform such structural transformations to the data after verifying the safety of the operation. Works such as [13] have investigated a general pointer analysis framework, which has been incorporated into techniques for hardware synthesis of pointers [10]. The same analysis information can be used to determine whether it is safe to transform the memory representation of data structures.…”

Section: Overall Design Flowmentioning

confidence: 99%

“…Exploration environments for determining an optimized application specific on-chip memory architectures are studied in [9,3]. More recently, in the context of C/C++ based synthesis, researchers have addressed the issue of finding reasonable hardware interpretations for dynamic memory allocation-related features [12,10].…”

Section: Introductionmentioning

confidence: 99%

Cache-efficient memory layout of aggregate data structures

Panda

Semeria

Micheli

2001

Proceedings of the 14th International Symposium on Systems Synthesis - ISSS '01

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We describe an important memory optimization that arises in the presence of aggregate data structures such as arrays and structs in a C/C++ based system design methodology. We present an algorithm for determining an optimized memory layout of such data. Our implementation consists of a pointer analysis and resolution phase, followed by memory layout optimization. Experiments on typical applications from the DSP domain result in up to 44% improvement in memory performance.

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“…The problem with dynamic memory allocation (malloc, free) and recursion is that the size of the memory required for an application is a priori unknown. Therefore, the synthesis of code involving dynamic memory allocation would require access to an operating system running in software or the generation of hardware allocators [44], [53]. Arbitrary control flow (e.g., due to goto statements) complicates the scheduling of operations even though it has been addressed [49].…”

mentioning

confidence: 99%

Resolution, optimization, and encoding of pointer variables for the behavioral synthesis from C

Semeria

Micheli

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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As designers may model mixed hardware-software systems using a subset of or ++, we present SpC, a solution to synthesize and optimize hardware models with pointers. In hardware, a pointer is not only the address of data in memory, but it may also reference data mapped to registers, ports, or wires. Pointer analysis is used to find the set of locations each pointer may reference in a program at compile time. In this paper, we address the problem of synthesizing and optimizing pointers to multiple variables or array elements. The value of the pointers are encoded and branching statements are used to dynamically access data referenced by pointers. A heuristic is used to efficiently encode the values of the pointers. Compiler techniques are also used to reduce storage before loads and stores. An implementation using the SUIF framework (Wilson et al., 1994; SUIF Compiler Framework) is presented, followed by some case studies and experimental results.

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Resolution of dynamic memory allocation and pointers for the behavioral synthesis from C

Cited by 13 publications

References 10 publications

Software Code Generation for the RVC-CAL Language

Software Code Generation for the RVC-CAL Language

Cache-efficient memory layout of aggregate data structures

Resolution, optimization, and encoding of pointer variables for the behavioral synthesis from C

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