Resist requirements in the era of resolution enhancement techniques

Abstract

At the heart of the tremendous advances of optical microlithography are the resists and the people who drove them to ever-higher performance. In 1980, a resist could reliably image around a k 1 of 1.0 to 0.8. Today without any other extreme RET, resists with anti-reflection coatings production imaging has extended resolution to 0.6 to 0.45 k 1 , effectively doubling the NA of the integrated imaging system. Manipulation of the interrelationships of the physics and chemistry of the imaging process has made this possible. History shows that resists must be designed to best utilize the image being formed in them and that a resist designed for one application may not work for another. This holds true for resolution enhancement techniques as well, for example the quality and brightness of a weak phase-shifted contact depends on the strength of its side lobe, however, if the side lobe is too bright it will print unless the resist is modified not to print it. Also as technology moves to smaller features severe proximity effects make it necessary to adjust resist performance to compensate for these effects. In this discussion we concentrate on the physical chemical effects that makes it possible to extend resolution using resolution enhancement techniques. We will concentrate on energy coupling into the film with high NA imaging at the diffraction limit, the reaction-diffusion reaction and the impact of acid and base diffusion in chemically amplified resists.Keywords: resist, resolution enhancement technique, RET, microlithography, chemically amplified resists, 248nm, 193nm, 157nm, simulator, antireflection coating, ARC IntroductionThe cost of designing and taking to market an advanced semiconductor product is becoming prohibitively expensive. Delaying delivery of production quantities of a new chip can cost millions of dollars in lost margins. Having to retool mask sets can cost more than $1 million at the 130nm technology node and beyond. Lost productivity of a $2 billion factory can cost in the neighborhood of $1 million per day, and use of these facilities, as laboratories must be reduced to a critical minimum. When considering that it costs each integrated-device-manufacturer (IDM) and foundry $300 to $500 million to develop a new manufacturing technology-node, and in addition that a state-of-the-art chip like a microprocessor at the 130nm node costs $18 million to design and at the 90nm node costs around $50 million to design with a significant portion being nonrecurring-engineering costs (NRE), it becomes imperative that product is designed so that it not only achieves yield entitlement quickly but does so with the desired performance specifications.

Low-Ea Chemical Amplification Resists for 193 nm Lithography

“…This observation was consistent with previous reports on the deprotection reactions of typical chemical amplification resists. [10][11][12][14][15][16] The activation energy E amp in the low-PEB-temperature region and the activation energy E diff in the high-PEB-temperature region were obtained from the slopes of each plot as shown by the dotted lines and the solid lines, respectively, in Fig. 6.…”

LER characterization and impact on 0.13-μm lithography for OPC modeling

“…gPAC can be calculated with the help of advanced photolithography simulators like KLA Prolith [9] for known optical parameters of the photolithography system and calibrated photoresist.…”

Unconventional methods for forming nanopatterns

“…Despite this success, optical photolithography is highly capital intensive and will face increasing cost pressures as the dimensions of devices are reduced beyond the 32 nm node [20] (a reality exemplified by tenets of Rock's Law, which state that the cost of building new fabrication facilities essentially doubles every four years) [21]. Lithography costs for integrated circuits (ICs) have grown exponentially for each technology node and show no sign of slowing [22].…”

“…The semiconductor industry first began commercial patterning of sub-100 nm features in 2003 using photolithographic processes based on 193 nm ultraviolet (UV) light (ArF excimer lasers) [18], and with related protocols is currently pushing the dimensions of physical gate lengths to $28 nm [19]. Despite this success, optical photolithography is highly capital intensive and will face increasing cost pressures as the dimensions of devices are reduced beyond the 32 nm node [20] (a reality exemplified by tenets of Rock's Law, which state that the cost of building new fabrication facilities essentially doubles every four years) [21]. Lithography costs for integrated circuits (ICs) have grown exponentially for each technology node and show no sign of slowing [22].…”