Reseeding-Based Test Set Embedding with Reduced Test Sequences

Kalligeros, Emmanouil; Kaseridis, D.; Kavousianos, X.; Nikolos, D.

doi:10.1109/isqed.2005.105

Cited by 13 publications

(21 citation statements)

References 8 publications

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“…we give the average number of gate area overhead of the two schemes under different L CRP . Table 3 compares the gate area overhead and the test application time of the proposed internal-response-based reseeding method against the previous mixed-mode BIST methods, including the ROM-based reseeding schemes [6,7] and the mapping-logic-based schemes [15,19]. Since the previous work in [6,7] does not report gate area overhead, we estimate their gate area overhead based on the reported controller architectures and the reported number of required ROM bits.…”

Section: Results Of Proposed Reseeding Schemementioning

confidence: 99%

“…Table 3 compares the gate area overhead and the test application time of the proposed internal-response-based reseeding method against the previous mixed-mode BIST methods, including the ROM-based reseeding schemes [6,7] and the mapping-logic-based schemes [15,19]. Since the previous work in [6,7] does not report gate area overhead, we estimate their gate area overhead based on the reported controller architectures and the reported number of required ROM bits. In Table 3, we highlight the cases where our methods (L CRP = 100 or 400) uses smaller area overhead or shorter test application time than those in [6,7,15,19].…”

Section: Results Of Proposed Reseeding Schemementioning

confidence: 99%

“…The storage of deterministic patterns in an on-chip ROM reduces the tester memory requirement and hence test-equipment cost. To further reduce the size of the ROM reseeding techniques [4,6,7,9,11,17] are widely adopted to compress the required test data into a few seeds of small size. The seeds can then be decompressed by an LFSR or similar hardware during test-application time.…”

Section: Introductionmentioning

confidence: 99%

“…The results also show that when longer test time is allowed for one seed to generate more pseudo-random patterns, both the number of required internal nets and gate-area overhead can be further reduced. Compared to the ROM-based reseeding methods in [6,7] and the mapping-logic-based BIST in [15,19], the proposed method results in much smaller gate-area overhead and shorter test-application time in most cases.…”

Section: Introductionmentioning

confidence: 99%

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Efficient LFSR Reseeding Based on Internal-Response Feedback

et al. 2014

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LFSR reseeding techniques are widely adopted in logic BIST to enhance fault detectability and shorten testapplication time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need a prohibitive amount of memory to store all required seeds. In this paper, a new LFSR reseeding technique is presented, which employs the responses of internal nets of the circuit itself as the control signals for changing LFSR states. A novel reseeding architecture containing a netselection logic module and an LFSR with some inversion logic is presented to generate all the required seeds on-chip in real time with no external or internal storage requirement. Experimental results on ISCAS and large ITC circuits show that the presented technique can achieve 100 % fault coverage with short test time by using only 0.23 -2.75 % of internal nets and with 2.35 -4.56 % gate area overhead on average for reseeding control without degrading the original circuit performance.

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Section: Results Of Proposed Reseeding Schemementioning

confidence: 99%

Section: Results Of Proposed Reseeding Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Efficient LFSR Reseeding Based on Internal-Response Feedback

et al. 2014

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“…Similarly to the solutions in [8,11], our approach reduces the AF of the CUT compared to conventional scan-based LBIST, by properly modifying the test vectors generated by the LFSR. Our approach is somehow similar to re-seeding techniques (e.g., that in [22]), to the extent that the sequence of test vectors is properly modified in order to fulfill a given requirement that, however, is not to increase FC (as it is usually the case for reseeding), but to reduce PD. The basic idea behind our approach (in its non-scalable version) was introduced in [23].…”

Section: Introductionmentioning

confidence: 99%

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Omaña

Rossi

Fuzzi

et al. 2017

IEEE Trans. VLSI Syst.

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Abstract-The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel, scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the Logic BIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target Fault Coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared to recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC.

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Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns

Al-Yamani

McCluskey

2010

J Electron Test

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Reseeding-Based Test Set Embedding with Reduced Test Sequences

Cited by 13 publications

References 8 publications

Efficient LFSR Reseeding Based on Internal-Response Feedback

Efficient LFSR Reseeding Based on Internal-Response Feedback

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns

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