Research on Topology and Policy for Low Power Consumption of Network-on-Chip with Multicore Processors

Fang, Juan; Lu, Jiajia; She, Chaojie

doi:10.1109/csci.2015.13

Cited by 5 publications

(2 citation statements)

References 9 publications

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“…The total power consumption from the interconnect can be estimated from the average communication distance. The total power to transmit a message of length can be calculated by router link P P total P   [11] Where P router and P link are the power used to transmit the message from source node to destination node through the router and link respectively. Figure 9 and 10 shows the total power consumption in the ring, mesh, cross-link mesh, reduce router in ring and mesh topologies.…”

Section: Results and Analysismentioning

confidence: 99%

Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture

Phing

Warip

Ehkan

et al. 2019

IJEECS

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<span>The size of the transistor has reached physical processor limitation in particular for traditional bus-based and point-to-point architecture in system-on-chip (SoC). Therefore, network-on-chip (NoC) was proposed as a solution. The performances required for the optimization of the NoC are low network latency, low power consumption, small area, and high throughput. However, recently the size of the NoC architecture has increased and the communication between cores to core become complicated. To overcome this disadvantages, topology plays an important role. In this paper, we reduce the number of the router in the 16 cores and 64 cores ring and mesh topologies by connected more numbers of node in each router. Result shows that reducing the number of the router in 64 cores ring topology outperforms the conventional topologies in term of area, power consumption, latency, and accepted packet rate. Reducing router in 64 cores ring topology decrease the average area, power consumption, latency, and increase the average accepted packet rate by 160.45%, 23.88%, 54.76%, and 223.88% over the 64 cores mesh, reducing router in mesh, ring, and cross-link mesh topologies.</span>

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Section: Results and Analysismentioning

confidence: 99%

Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture

Phing

Warip

Ehkan

et al. 2019

IJEECS

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show abstract

“…Regarding [11] has proposed an RRCIES topology based on mesh topology. RRCIES has reduced the average power consumption in Network-on-Chip (NoC).…”

Section: Related Workmentioning

confidence: 99%

Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture

et al. 2017

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In essence, Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed as a design solution to System-on-Chip (SoC). The routing algorithm, topology and switching technique are significant because of the most influential effect on the overall performance of Network-on-Chip (NoC). Designing of large scale topology alongside the support of deadlock free, low latency, high throughput and low power consumption is notably challenging in particular with expanding network size. This paper proposed an 8x8 XX-Torus and 64 nodes XX-Ring topology schemes for Network-on-Chip to minimize the latency by decrease the node diameter from the source node to destination node. Correspondingly, we compare in differences on the performance of mesh, full-mesh, torus and ring topologies with XX-Torus and XX-Ring topologies in term of latency. Results show that XX-Ring outperforms the conventional topologies in term of latency. XX-Ring decreases the average latency by 106.

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A survey of recent contributions on low power NoC architectures

Ofori-Attah

Agyeman

2017

2017 Computing Conference

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Research on Topology and Policy for Low Power Consumption of Network-on-Chip with Multicore Processors

Cited by 5 publications

References 9 publications

Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture

Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture

Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture

A survey of recent contributions on low power NoC architectures

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