Remote-charge-scattering limited mobility in field-effect transistors with SiO2 and Al2O3∕SiO2 gate stacks

Abstract

We examined, both experimentally and theoretically, the mobility reduction in metal-insulator-semiconductor field-effect transistors (MISFETs) limited by remote charge scattering. The accuracy of the mobility calculations was confirmed by agreement with experiments on MISFETs with pure SiO2 gate dielectrics, in which mobility is reduced due to scattering from the depletion charges in the polycrystalline silicon gate. In MISFETs with Al2O3∕SiO2 gate stacks, we could not identify the contributions from the remote phonon scattering by using low-temperature measurements of the mobility. The experimental mobility reduction is explained by a model in which both negative and positive charges are located at the Al2O3∕SiO2 interface. According to this model, the mobility increases with the interfacial SiO2 thickness. We confirmed this by fabricating MISFETs with various interfacial SiO2 thicknesses.

Low-Temperature Fabricated TFTs on Polysilicon Stripes

“…We attribute this mobility enhancement to the use of a thick high-quality SiO 2 gate dielectric [26] in contrast to the earlier used thin Al 2 O 3 [15]. Al 2 O 3 has also shown to yield lower mobilities in the case of MOS transistors on monocrystalline Si [27].…”

Silicon diffusion control in atomic-layer-deposited Al2O3/La2O3/Al2O3 gate stacks using an Al2O3 barrier layer

“…However, in sub-45-nm complementary metal oxide semiconductor (CMOS) technology, the scaling of SiO 2 gate dielectric thickness leads to an unacceptable gate leakage current, which affects the reliability of the device and causes an increase in static power dissipation. Therefore, new kinds of dielectric materials with high permittivity are needed to replace the traditional SiO 2 gate dielectric to obtain a smaller equivalent oxide thickness (EOT) in the CMOS industry [1,2]. Presently, the use of HfO 2 (k~13 to 20) as the gate dielectric in the high-k/metal gate structure has been successfully applied to MOSFET fabrication and is gradually replacing the traditional SiO 2 /poly-Si gate structure [3].…”

Electronic devices fabricated at CMOS backend-compatible temperatures

“…It should be emphasized that in this work a thin (16 nm [151] as due to the remote charge scattering of the charge carriers from fixed charges at the mentioned interfaces and in the volume of Al 2 O 3 gate dielectric. To reduce the influence of fixed charges it is proposed to use a controllably grown 1-nm thick interfacial SiO 2 layer on the crystallized film [151].…”

“…It is reported a significant improvement in TFT performance when using silicon oxide as a gate dielectric instead of Al 2 O 3 [151]. To evaluate the effect of silicon oxide utilization on the same laser crystallized silicon films, the devices with SiO 2 gate, deposited at low-temperatures, were investigated.…”

“…To reduce the influence of fixed charges it is proposed to use a controllably grown 1-nm thick interfacial SiO 2 layer on the crystallized film [151]. Figure 6.17 represents the front-/ bottom-gate field-effect mobility for holes at different laser crystallization energies.…”