Reliable and low cost wafer level packaging. Process description and qualification testing results for wide area vertical expansion (WAVE/sup TM/) package technology

Abstract

BiographyVern Solberg has more than twenty-five years of experience in the design and manufacturing of electronic products. Founder of NuGrafix Group, the first design and engineering service company dedicated to SMT. He also served as Manager of Design Engineering for SCI Systems, a multinational assembly service company for eight years followed by five years as the Director of Advanced Manufacturing Technology with Tessera, the developer of the PBGA package technology. His primary activities are related to application engineering and assembly process development, serving as a technical advisor to in-house as well as OEM customer engineers and design specialists. Mr. Solberg is a member of IPC, IMAPS, and SMTA, focusing on product "Design for Manufacturing". AbstractA number of companies around the world are developing or have begun offering devices processed and packaged in the wafer format. Most of these competing concepts involve the creation of a redistribution layer over the face of the chip, a method long employed by IBM in the development of its well known flip-chip C4 processes. Wafer level packaging has the potential for transforming IC packaging from a labor ,intensive process of making wire bonds one-at-a-time on individual die, to a batch process, much like wafer fab. Tessera has developed a unique approach to wafer level packaging that provides a physically robust, compliant structure while offering significant cost reduction through a unique method of mass termination and encapsulation. In this paper, the authors will describe the materials and process developed for utilizing 'wide area vertical expansion' (WAVETM), producing what may prove to be the most reliable chip-size package available. To back-up this rather bold statement, the environmental test program description will be outlined and test data offered for review.