Reliability study of MANOS with and without a SiO&lt;inf&gt;2&lt;/inf&gt; buffer layer and BE-MANOS charge-trapping NAND flash devices

Liao, Chien-Wei; Lai, Sheng-Chih; Lue, Hang-Ting; Yang, Ming-Jui; Shen, C.-H.; Lue, Yi-Hsien; Huang, Ya-Chi; Hsieh, Jung-Yu; Wang, Szu-Yu; Luo, Guang-Li; Chien, Chao–Hsin; Hsieh, Kuang-Yeu; Liu, Rich; Lu, Chih‐Yuan

doi:10.1109/vtsa.2009.5159335

Cited by 4 publications

(2 citation statements)

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“…Moreover, for MLC operation in Solid State Drives (SSD) these memories will also require excellent endurance along with large memory window. Various solutions have been proposed, such as engineered tunnel oxide [1]- [4] and blocking dielectric [5]; however achieving large memory window (>8 V) without sacrificing endurance and retention is still problematic.…”

Section: Introductionmentioning

confidence: 99%

High Performance THANVaS Memories for MLC Charge Trap NAND Flash

Suhane

bosch

Arreghini

et al. 2011

2011 3rd IEEE International Memory Workshop (IMW)

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In this paper we investigate THANOS and THANVaS memory devices featuring a 2 nm HfO2 capping layer on top of the Al2O3 blocking dielectric. Furthermore, we benchmark these devices against reference TANOS and TANOS with variable tunnel oxide thickness (TANVaS), respectively. It is found that HfO2 capping layer improves erase saturation level due to its better electron blocking capabilities during erase operation, as also confirmed by simulations. As a result of improved erase saturation, THANVaS device shows excellent performance of 9.5 V memory window with flat endurance up to 10 4 cycles and improved high temperature retention.

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Section: Introductionmentioning

confidence: 99%

High Performance THANVaS Memories for MLC Charge Trap NAND Flash

Suhane

bosch

Arreghini

et al. 2011

2011 3rd IEEE International Memory Workshop (IMW)

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“…This allows the TANOS device to operate under higher electric¯eld, strong enough to cause electron detrapping from the SiN traps. Although the electron detrapping rate is slower than the hole injection rate in BE-SONOS, 9 but since gate injection is virtually completely stopped, fast erasing is possible by operating in higher electric¯eld.…”

Section: Charge Trapping (Ct) Devicesmentioning

confidence: 99%

Nonvolatile Memory Technology: A Driver to Future Nanoelectronics

2012

SPIN

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Flash memory has served as an important technology driver due to its many new applications. Despite the fact that NAND°ash has out run lithography and other scaling barriers and thus is facing steep challenges, several innovative solutions are being developed to carry its momentum, and it continues to serve as a technology driver in the nanoelectronics era. New devices that are not based on charge storage, on the other hand, are promising to further boost system performance by o®ering low-power, high-density, and fast latency storage. These new developments should provide the next generation memory and storage solutions that will elevate system performance to a new level.The elegant NAND°ash architecture allows a minimum size memory cell consisting of a single

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Physical modeling of program and erase speeds of metal–oxide–nitride–oxide–silicon cells with three-dimensional gate-all-around architecture

Lee

Yang

Jung

et al. 2013

Jpn. J. Appl. Phys.

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We present an investigation of the program and erase speed characteristics of three-dimensional (3D) gate-all-around (GAA) metal–oxide–SiN X –oxide–silicon (MONOS) cells. The effect of the tunneling oxide layer thickness in 3D GAA MONOS cells has been experimentally investigated and studied by 3D technology computer-aided design (TCAD) simulation. In particular, we considered physical parameters such as trap density, capture cross section, and trap level in order to analyze the physical properties of the silicon nitride layer. Simulation results indicated that the trap density significantly affects the program efficiency compared with other physical parameters, and the trap level mainly affects the erase efficiency. From these simulation results, we confirmed from the experimental results that the modeling accuracy is about 80%. Moreover, the simulation results for the program and erase speeds of the GAA MONOS cells were in reasonable agreement with experimental results.

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Reliability study of MANOS with and without a SiO<inf>2</inf> buffer layer and BE-MANOS charge-trapping NAND flash devices

Cited by 4 publications

References 1 publication

High Performance THANVaS Memories for MLC Charge Trap NAND Flash

High Performance THANVaS Memories for MLC Charge Trap NAND Flash

Nonvolatile Memory Technology: A Driver to Future Nanoelectronics

Physical modeling of program and erase speeds of metal–oxide–nitride–oxide–silicon cells with three-dimensional gate-all-around architecture

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