Physical modeling of program and erase speeds of metal–oxide–nitride–oxide–silicon cells with three-dimensional gate-all-around architecture

Abstract

We present an investigation of the program and erase speed characteristics of three-dimensional (3D) gate-all-around (GAA) metal–oxide–SiN X –oxide–silicon (MONOS) cells. The effect of the tunneling oxide layer thickness in 3D GAA MONOS cells has been experimentally investigated and studied by 3D technology computer-aided design (TCAD) simulation. In particular, we considered physical parameters such as trap density, capture cross section, and trap level in order to analyze the physical properties of the silicon nitride layer. Simulation results indicated that the trap density significantly affects the program efficiency compared with other physical parameters, and the trap level mainly affects the erase efficiency. From these simulation results, we confirmed from the experimental results that the modeling accuracy is about 80%. Moreover, the simulation results for the program and erase speeds of the GAA MONOS cells were in reasonable agreement with experimental results.

Overcoming bit loss mechanism in self‐amplified multilevel silicon‐oxide‐nitride‐oxide‐silicon memory cell

“…The trap concentration considered in this work was fixed at 10 19 cm −3 with trap energy level 1 eV. The considered trap energy level is consistent with the work reported by authors in Reference 43. Models used for the analysis of the flash device are consistent with the published literature 44 and calibrated against the experimental results 45…”

“…The simulations were carried out using field, and concentration-dependent mobility models, drift-diffusion transport phenomena, and Shockley-Read-Hall model. 42 The high field phenomenon, like the hot electron effect, will not be prevalent at an applied drain bias of 1 V. 43 The transient analysis was performed to analyze the trapping and detrapping of the charge carriers in the nitride layer. 42 The charge transport through the dielectric layers has been considered through the Poole-Frenkel model.…”

Extraction of Nitride Trap Profile in 3-D NAND Flash Memory Using Intercell Program Pattern

“…where the effective mass (m * n) and the capture-cross section of electron in the SiN layer (σn) are 0.42m0 and 1×10 -14 cm 2 , respectively [11], [32].…”

Threshold voltage variation depending on single grain boundary and stored charges in an adjacent cell for vertical silicon–oxide–nitride–oxide–silicon NAND flash memory

“…Channel doping concentration N A (cm −3 ) 1 0 16 S=D doping concentration N D (cm −3 ) 1 0 20 Grain boundary trap states N GB 23,24) (cm −2 eV −1 ) 1 0 12 -10 14 energy levels of electrons and holes were assumed to be 1.2 and 2.5 eV, respectively. 25,26) The program bias condition was a 16 V single pulse with a 1 ms hold time, and the read bias increased up to 4 V at various V d values. The program operation of the adjacent cell was performed to examine the influence of stored charges in the adjacent cell, as shown in Fig.…”