2017 IEEE International Interconnect Technology Conference (IITC) 2017
DOI: 10.1109/iitc-amc.2017.7968972
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Reliability of hybrid bond interconnects

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Cited by 10 publications
(4 citation statements)
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“…In addition to TSVs, hybrid bonding techniques that involve both Cu bonding and oxide bonding have also been developed for 3DIC applications. Typically, oxide-oxide bonding occurs at room temperature before the temperature is raised to around 300 • C for Cu-Cu bonding [12][13][14][15][16]. The requirement to elevate the temperature is attributed to the higher coefficient of thermal expansion (CTE) of Cu compared to the surrounding SiO 2 [17].…”
Section: Introductionmentioning
confidence: 99%
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“…In addition to TSVs, hybrid bonding techniques that involve both Cu bonding and oxide bonding have also been developed for 3DIC applications. Typically, oxide-oxide bonding occurs at room temperature before the temperature is raised to around 300 • C for Cu-Cu bonding [12][13][14][15][16]. The requirement to elevate the temperature is attributed to the higher coefficient of thermal expansion (CTE) of Cu compared to the surrounding SiO 2 [17].…”
Section: Introductionmentioning
confidence: 99%
“…The success of the hybrid bonding process relies on the final chemical mechanical polishing (CMP) stage of the copper [18,19]. During this stage, it is essential to achieve a flat oxide surface while ensuring that the copper is slightly recessed from the oxide Materials 2024, 17, 2150 2 of 10 surface [12][13][14]. The degree of "Cu recess" required depends on several factors, including the bonding temperature [20,21], expected service temperature, and the depth of TSV (Cu film thickness).…”
Section: Introductionmentioning
confidence: 99%
“…The recess of Cu pads, which is typically a few nanometers [16], should be smaller than their expansions to ensure proper contact during annealing. This allows for oxide-oxide bonding to take place at room temperature before raising the temperature to approximately 250-300 • C for Cu-Cu bonding [17][18][19][20]. The requirement to elevate the temperature is attributed to the higher coefficient of thermal expansion (CTE) of Cu compared to the surrounding SiO 2 [21].…”
Section: Introductionmentioning
confidence: 99%
“…Currently, chips and wafers with different functions are manufactured separately and vertically stacked via hybrid bonding processes, which offer a promising solution for three-dimensional (3D) integration to continue Moore's law [1][2][3]. The wafer-level hybrid bonding of Cu and silicon oxides has already been applied in the mass-production stacking of back-illuminated CMOS image sensors (BI-CIS) [4].…”
Section: Introductionmentioning
confidence: 99%