Reliability investigation upon 30nm gate length ultra-high aspect ratio FinFETs

FinFET reliability study by forward gated-diode generation–recombination current

“…This W/L ratio will be further used to determine the detailed FinFET height and channel length in our next study. To characterize the interface states distribution, the forward gateddiode current method is used to measure the generationrecombination (G-R) current as described in [9][10][11][12]. As has been reported that the top surface of a FinFET has much fewer interface states than the sidewall due to surface roughness [11], the interface contribution from the top surface is ignored.…”

“…While continuous improvements in fabrication processes and device performances have been reported, reliability issues of FinFETs have received less attention. In recent years, some studies of hot-carrier effect and interface states generation have been reported [9][10][11]. Most studies showed that hot-carrierinduced degradation can be observed in these devices and the degradation of maximum transconductance becomes more serious with decreasing fin width [9].…”

“…Most studies showed that hot-carrierinduced degradation can be observed in these devices and the degradation of maximum transconductance becomes more serious with decreasing fin width [9]. However, other reports showed that ultra-high aspect ratio (such as height/width = 7) enhances both the electrical characteristics and the reliability of a FinFET [10]. In general, the interface state distribution at the top interface of a FinFET is observed to be much lower than that at the fin sidewall [11].…”

Growth of Samarium-Substituted Epitaxial Bismuth Ferrite Films by Chemical Vapor Deposition

“…Batch-to-batch inconsistency is another issue that makes the use of CSD challenging in semiconductor manufacturing. Film growth by CSD needs high-temperature processing to remove solvents and decomposition of precursors; high-temperature processing is undesirable for the semiconductor and optoelectronic industry. , In the context of the advent of a 3 nm process node having a critical dimension below 10 nm, it will be challenging for wet process-based techniques like CSD to be able to controllably coat such small dimensions with a high aspect ratio (>7:1) . In addition, there are ever-increasing challenges to coat three-dimensional multigate transistor structures in the future, and the use of the CSD technique to grow thin films for very large-scale integration (VLSI) seems challenging .…”

“…55,56 In the context of the advent of a 3 nm process node having a critical dimension below 10 nm, 57 it will be challenging for wet process-based techniques like CSD to be able to controllably coat such small dimensions with a high aspect ratio (>7:1). 58 In addition, there are ever-increasing challenges to coat threedimensional multigate transistor structures in the future, and the use of the CSD technique to grow thin films for very large-scale integration (VLSI) seems challenging. 59 The vaporbased CVD technique is preferable for such demanding applications.…”