Reliability improvement of 9 nm-node Cu/low-k interconnects

Abstract

We have studied electromiyation (EM) and stress-induced voiding (SV) behaviors based on our 90nm-node Cuilow-k interconnect processes, and demonstrated successful improvement of the interconnect reliability. In EM study wide bimodal failure distribution was found only in the particular EM test structure. We identified that it caused by the lack of wettability between Cu and the barrier metal in the vias, and demonstrated that the ,optimization of the barrier metal thickness could suppress it. In SV behavior, we revealed a mechanism of the voiding under the vias that was due to the initial existence of the nuclei of the void before high temperature storage test. The failure mode was suppressed by optimizing preheat temperature of M2 barrier metal deposition.interconnects for 90nm-node system LSIs. Dimensions of both minimum line width and space are 120nm for M I, and 140nm for M2 to M5 with minimum via size of 140ntn. Here, the via-first trench-last Cu dual-damascene process was applied with low-k dielectrics patterned by high NA ArF lithography. Dielectrics structures were Si02iSiC for the MI inna-level and the SiOCiSi02 hybrid sttucture with S i c diffusion barrier dielectric for the M2 to M5 intra-and inter-level. The electrochemical deposited (ECE) Cu on physical vapor deposited (PVD) Cu seed that lies on Td?

Cu Wettability and Diffusion Barrier Property of Ru Thin Film for Cu Metallization

“…4 TaN currently used as a diffusion barrier can be replaced with Ta/TaN to improve the adhesion strength of Cu, and thus enhance the electromigration lifetime. [6][7][8] However, continued aggressive reduction in transistor dimensions requires a new generation of underlayers with low resistivity and better adhesion property with Cu for low contact resistance and long electromigration lifetime.…”

Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes

“…This success of the simpler and hence, manufacturable integration with less materials and interfaces is attributed to the capability of modern dry etching tools which have controllability and uniformity across the wafer enough to support the pattern definition in the monolithic damascene scheme. Another example to show the strong dependency on the tool/material/process capability and readiness is the across-the-wafer non-uniformity of modern CMP tools which so far seem unable to support the Hard Mask Retention scheme for the use of ULK at the trench level for the 65 nm node BEOL technologies in the manufacturing phase, although a bunch of damascene schemes have been reported [18][19][20][21][22][23][24].. Thus, discussions on possibility of implementation of ULK in the 45 nm node BEOL must be made on certain assumptions about the tool capability/readiness and limitation for manufacturing [25][26][27].…”

Design and analysis of 45 nm low power 32 kb embedded static random access memory (SRAM) cell

“…Before developing our discussion, we have to comment on the merit of lowering VM potential. Various methods of controlling source line potential to reduce leakage current have been reported so far (International Technology Roadmap for semiconductors, 2001; Matsumoto et al, 2003;Nii et al, 1998;Oh et al, 2003;Osada et al, 2001Osada et al, , 2003Sze, 1981). Lowering the V DD source line has the advantage of reducing the sub threshold leakage current of the PMOS load transistor.…”