Reliability evaluation of von neumann multiplexing based defect-tolerant majority circuits

Bhaduri, D.; Shukla, Sandeep K.

doi:10.1109/nano.2004.1392432

Cited by 6 publications

(2 citation statements)

References 8 publications

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“…The main contribution of this paper lies in combining a novel scaling model (capturing the wire dominated regimes of interest) with traditional reliability analysis to tackle these questions. This might be viewed in contrast to research initiated by [9] tackling computability with unreliable devices, but ignoring device and wiring overheads, see e.g., [10,11]. By considering wire dominated regimes our work also differs from previous work considering reliability and overhead models based solely on gate count see e.g., [12].…”

Section: Introductionmentioning

confidence: 92%

Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When Do Smaller Less Reliable Devices Make Sense?

Zykov

Veciana

2008

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

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Section: Introductionmentioning

confidence: 92%

Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When Do Smaller Less Reliable Devices Make Sense?

Zykov

Veciana

2008

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

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“…As a result, von Neumann's multiplexing technique has received attention again [14]. A wealth of papers that reported the performance analysis of multiplexing technique have been published and, among them, the most attention was paid to NAND multiplexing [15][16][17][18] and majority multiplexing [19][20][21], first proposed by von Neumann. The multiplexing technique has been studied as an effective fault-tolerant technique for protection against the increasing transient faults in nanoelectronic circuits [22][23][24][25].…”

Section: Introductionmentioning

confidence: 99%

XOR Multiplexing Technique for Nanocomputers

Diao

Chen

et al. 2020

Applied Sciences

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In emerging nanotechnologies, due to the manufacturing process, a significant percentage of components may be faulty. In order to make systems based on unreliable nano-scale components reliable, it is necessary to design fault-tolerant architectures. This paper presents a novel fault-tolerant technique for nanocomputers, namely the XOR multiplexing technique. This hardware redundancy technique is based on a numerous duplication of faulty components. We analyze the error distributions of the XOR multiplexing unit and the error distributions of multiple stages of the XOR multiplexing system, then compare them to the NAND multiplexing unit and the NAND multiplexing multiple stages system, respectively. The simulation results show that XOR multiplexing is more reliable than NAND multiplexing. Bifurcation theory is used to analyze the fault-tolerant ability of the system and the results show that XOR multiplexing technique has a high fault-tolerant ability. Similarly to the NAND multiplexing technique, this fault-tolerant technique is a potentially effective fault tolerant technique for future nanoelectronics.

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Tools and Techniques for Evaluating Reliability Trade-Offs for Nano-Architectures

Bhaduri

Shukla

Nano, Quantum and Molecular Computing

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It is expected that nano-scale devices and interconnections will introduce unprecedented level of defects in the substrates, and architectural designs need to accommodate the uncertainty inherent at such scales. This consideration motivates the search for new architectural paradigms based on redundancy based defect-tolerant designs. However, redundancy is not always a solution to the reliability problem, and often too much or too little redundancy may cause degradation in reliability. The key challenge is in determining the granularity at which defect tolerance is designed, and the level of redundancy to achieve a specific level of reliability. Analytical probabilistic models to evaluate such reliability-redundancy trade-offs are error prone and cumbersome, and do not scale well for complex networks of gates. In this thesis we develop different tools and techniques that can evaluate the reliability measures of combinational circuits, and can be used to analyze reliability-redundancy trade-offs for different defect-tolerant architectural configurations. In particular, we have developed two tools, one of which is based on probabilistic model checking and is named NANOPRISM, and another MATLAB based tool called NANOLAB. We also illustrate the effectiveness of our reliability analysis tools by pointing out certain anomalies which are counter-intuitive but can be easily discovered by these tools, thereby providing better insight into defecttolerant design decisions. We believe that these tools will help furthering research and pedagogical interests in this area, expedite the reliability analysis process and enhance the accuracy of establishing reliability-redundancy trade-off points. List of Tables 2.1 Logic compatibility function for a NAND gate with all possibilities. . .

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Reliability evaluation of von neumann multiplexing based defect-tolerant majority circuits

Cited by 6 publications

References 8 publications

Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When Do Smaller Less Reliable Devices Make Sense?

Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When Do Smaller Less Reliable Devices Make Sense?

XOR Multiplexing Technique for Nanocomputers

Tools and Techniques for Evaluating Reliability Trade-Offs for Nano-Architectures

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