Reliability consequences of the chip-package interactions

Driel, W.D. van

doi:10.1109/eptc.2009.5416512

Cited by 6 publications

(4 citation statements)

References 13 publications

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“…A recent summary of CPI failure modes including delamination of BEOL dielectric layers, passivation cracks, metal shift, inter-metallic shorts, damage under the bump can be found in [1] by van Driel. White Bumps are the prime indicator of localized cracks or delamination in the dielectric layers in an organic laminate-based electronic package.…”

Section: Introductionmentioning

confidence: 99%

Chip Package Interaction: An Experiment Study on White Bump Mitigation Using Flat Laminates

Pan

Zitz

Questad

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Chip-Package Interaction (CPI) related failure risk has increased in organic laminate-based electronic packages fueled in part by certain industry-segments' requirements for larger silicon die size and signal performance. CPI-related stresses increase directly with radial distance from the center of the die, known as distance from the neutral-point (DNP). The resulting risk of local delamination (White Bumps, WBs) in the silicon back-end-of-line (BEOL), fracture of C4 interconnections and failure of underfill and chip ultimately impact electronic package reliability. Named from the notable visible white halo or circle around a C4 in a CSAM (C-Mode Scanning Acoustic Microscopy) image, WBs are the prime indicator of a CPI-related failure event in an organic laminatebased electronic package.Laminate and BEOL design, specifically wiring proximal to the C4 interconnection, are known to influence WB reliability. In this paper we specifically study the effect of laminate and BEOL design on the generation of white bumps. Four different chip designs, some of which are more susceptible to WBs than others are mated with both productdesign and "flat" laminates, or laminates consisting of only a core and single copper layer on each side. Our ultimate goal is to highlight the silicon & laminate designs' ability to modulate WB occurrences, to create design ground-rules thereby relaxing the cost and facilitating the development of package assembly solutions.A comprehensive experiment was carried out to achieve these goals. As companion test vehicles to product laminates, four different flat laminate (0-2-0) designs were fabricated with several different core materials to both segregate the effect of laminate wiring design and modulate the overall laminate coefficient of thermal expansion (CTE). Four separate chip designs were used to study the effect of the back end of line design.Thermal stress was induced in the experiment using a high-cooling rate or "hammer" chip-join (HCJ) reflow profile which drives a higher C4 shearing stress than with the nominal profile. The occurrence of WBs was then monitored while the test vehicles were repeatedly subjected to the hammer profile in a controlled hammer thermal cycling (HTC) process. Diagnostic measurements including 3D Surface Metrology and CSAM were performed after each HTC cycle to monitor both laminate warpage and WB occurrence respectively. White Bump evolution was statistically analyzed and correlated to each die design, laminate cross-sectional design and CTE. Results demonstrated the importance of laminate design in that the flat laminates consistently lead to fewer WBs than product laminates. Lower-CTE laminates also result in fewer WBs than product laminates. IntroductionChip-package interaction thermo-mechanical stresses (CPI Stress) exist in electronic packages due to the coefficient of thermal expansion mismatch among the different materials used to fabricate the package and critical temperatures (curing) at which these materials are processed. Such stresses can reach th...

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Section: Introductionmentioning

confidence: 99%

Chip Package Interaction: An Experiment Study on White Bump Mitigation Using Flat Laminates

Pan

Zitz

Questad

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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“…Recently, for high device density, the size of micro-scale structures on ICs such as micro-bumps [4], [5] or throughsilicon vias (TSVs) [6] are reduced to <10 μm. As 3D-ICs have more complex structures and smaller device sizes, accurate and precise surface imaging becomes critical to prevent device failures [7]- [10].…”

Section: Introductionmentioning

confidence: 99%

785-nm Frequency Comb-Based Time-of-Flight Detection for 3D Surface Profilometry of Silicon Devices

Kwak

Ahn

et al. 2022

IEEE Photonics J.

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Three-dimensional integrated circuits (3D-ICs) are becoming more significant in portable devices, autonomous vehicles, and data centers. As the demand for highly integrated and high-performance semiconductor devices grows, recent 3D integration technologies focus on lowering the size of the microstructures on such devices for high density. In order to inspect the 3D semiconductor devices, it is critical to measure the heights, depths, and overall surface profiles of the micro-structures made with silicon materials. Here, we demonstrate precise surface imaging for silicon devices by using a femtosecond mode-locked laser centered at 785 nm wavelength and an electro-optic sampling-based time-of-flight detection method with sub-10nanometer axial precision. We could successfully measure the surface profiles as well as the step heights of silicon wafer stacks and micro-scale structures on silicon substrates.

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“…The decreasing feature sizes and increasing power/current and performance requirements of the current and next generation IC devices has led to need for materials changes in the chip: to weaker low-k and ultra low-k films (ULK); increases in the number of fine pitch Cu wiring levels; use of more stressful under bump metallurgy (UBM)/lead-free C4 bumps and organic laminates [1][2]. All of these contribute to a weaker and highly stressed packaged part susceptible to white C4 bumps during the assembly or chip-join processing and/or during reliability stressing of the parts.…”

Section: Introductionmentioning

confidence: 99%

Role of FBEOL Al pads and hard dielectric for improved mechanical performance in lead-free C4 products

Misra

Daubenspeck

Wassick

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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One of the major reliability concerns of current and next generation integrated circuits is mechanical failure due to stresses induced by the chip-package interactions (CPI). The packaged parts are subjected to thermal-mechanical stresses due to a mismatch of the coefficient of thermal expansion of the Si, lead-free C4 bumps, and the organic flip-chip substrate leading to mechanical delamination or cracking in the weaker low-k/ultra-low K films within the chip. This work discusses the role of Aluminum (Al) pads in the far-back-end -of-line (FBEOL) levels of the chip in CPI stress mitigation of the weak low-k and ultra-low k (ULK) BEOL levels. The affect of the Al pad thickness, size and shape on the CPI stresses have been studied by means of 3D mechanical finite element analysis. "White C4" bump data showing the benefits of increasing the thickness of the Al pads and growing the Al pad size to be larger than the under bump metallurgy (UBM) diameter in alleviating detrimental stresses from the weak BEOL levels is also been discussed in the paper. This paper also outlines through mechanical modeling and "white C4" bump data the reduction in CPI stresses in the weaker BEOL levels with increasing thickness of the FBEOL hard dielectric.

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Reliability consequences of the chip-package interactions

Cited by 6 publications

References 13 publications

Chip Package Interaction: An Experiment Study on White Bump Mitigation Using Flat Laminates

Chip Package Interaction: An Experiment Study on White Bump Mitigation Using Flat Laminates

785-nm Frequency Comb-Based Time-of-Flight Detection for 3D Surface Profilometry of Silicon Devices

Role of FBEOL Al pads and hard dielectric for improved mechanical performance in lead-free C4 products

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