Reliability Calculation With Respect to Functional Failures Induced by Radiation in TMR Arm Cortex-M0 Soft-Core Embedded Into SRAM-Based FPGA

Benites, Luis; Benevenuti, Fabio; Oliveira, Ádria Barros de; Kastensmidt, Fernanda Lima; Added, N.; Aguiar, Vitor A. P.; Medina, N. H.; Guazzelli, Marcilei A.

doi:10.1109/tns.2019.2921796

Cited by 20 publications

(5 citation statements)

References 16 publications

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“…Hence, it considerably simplifies the data copying program and minimizes performance penalties. This flow is specifically interesting in some designs that make use of hardware redundancy strategies, such as TMR (Triple Modular Redundancy) [25,26]. As described in Figure 6, it consists of several steps:…”

Section: Location Constraint Flow: Generate Homogeneous Implementatio...mentioning

confidence: 99%

A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices

et al. 2022

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This paper proposes a methodology to access data and manage the content of distributed memories in FPGA designs through the configuration bitstream. Thanks to the methods proposed, it is possible to read and write the data content of registers without using the in/out ports of registers in a straightforward fashion. Hence, it offers the possibility of performing several operations, such as, to load, copy or compare the information stored in registers without the necessity of physical interconnections. This work includes two flows that simplify the designing process when using the proposed approach: while the first enables the protection or unprotection of writing on different partial regions through the bitstream, the second permits homogeneous instances of a design implemented in different reconfigurable regions to be obtained without losing efficiency. The approach is based and has been physically validated on the ZYNQ from Xilinx, and when using partially reconfigurable designs, it does not affect the hardware overhead nor the maximum operating frequency of the design.

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Section: Location Constraint Flow: Generate Homogeneous Implementatio...mentioning

confidence: 99%

A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices

et al. 2022

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“…Suppose the plane wave is incident on a rough surface, and the incident surface is assumed to be in the x − z plane, so φ i = 0. The electric and magnetic fields of the incident wave are, respectively, as follows [21,22]:…”

Section: Electromagnetic Occlusion Algorithmmentioning

confidence: 99%

Electromagnetic Occlusion Algorithm Based on FPGA and Panel Grouping and Its Optimization

Cao

2021

Wireless Communications and Mobile Computing

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With the development of digital signal processing and advanced algorithms, real-time signal processing based on FPGA and DSP is suitable for high-speed radar signal processing. With the rapid development of science and technology, war has entered the information age guided by high technology, and advanced science and technology has played a vital role in the trend of war. In recent years in the modern war, many countries invest a lot of research effort on the stealth technology, and advanced stealth technology can use a variety of technical means to alter or weaken the feature information of the target, confuse the enemy radar detection system effectively, reduce the chance of being detected to the largest extent, and prolong the lifecycle of aircraft and weapons. This research mainly discusses the electromagnetic occlusion algorithm and its optimization based on FPGA and panel grouping. The FPGA model selected for this study is XC6VLX240T-1FF1156I. Because the amount of data processed here is not very large, the cache part directly uses the on-chip storage resources of the FPGA, and the AD device is used to perform analog-to-digital/digital-to-analog conversion on the signal and perform digital up-down conversion. For a facet, it is necessary to first verify whether it is a bright facet and set the flag to mark it, then the facet needs to be occluded with the triangular facet marked as a bright facet, and all bright facets that have been marked need to be traversed. Open MP parallelization of the occlusion algorithm is as follows: The physical optics method is used to calculate the target RCS, and the focus of parallelism is placed on the part with a large amount of calculation. When using Open MP to design a program on a multicore computer, each group is assigned a thread to give full play to the core computing power. The total field is scattered and superimposed by each surface element. This part uses the parallel processing mode of Open MP, which allows the panel judgment in the group to be carried out at the same time. This part requires schedule to allocate resources and use different parallel mechanisms for different calculations to optimize debugging. In the angular range where there is multiple scattering at 0 ° ≤ φ ≤ 90 ° , the calculation results and the measurement results are in good agreement, and when the two planes are simulated with 1820 triangular faces, the fast multiple scattering in this paper only needs 4 minutes. This research has realized the general radar signal processing method based on FPGA structure, and the design has important engineering realization significance.

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“…The triple modular redundancy (TMR) is a longtime-used approach for mitigating various kinds of faults. TMR uses three copies of a circuit and hence provides an excellent level of reliability, but it requires a large area and suffers from high power consumption [13]- [15]. To reduce the area and power overheads, some approaches use double modular redundancy (DMR) [16].…”

Section: Introductionmentioning

confidence: 99%

A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications

Shukla

Ray

2022

IEEE Access

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Radiation can affect the correct behavior of an electronic device. Hence, the microprocessors used for space missions need to be protected against fault. TMR (Triple modular redundancy) is used for mitigating various kinds of faults in an electronic circuit. Although TMR provides an excellent level of reliability, it takes a large area and suffers from high power consumption. To reduce the area and power overheads DMR (double modular redundancy) is used. The DMR approach significantly reduces the resource overhead but it also reduces the performance by imposing timing penalty. Various methods have been proposed since the incarnation of TMR and DMR, but the resource overhead is still a challenging issue. Hence, in this work, a new DMR based reconfigurable quad-core RV32IM processor architecture is proposed for fault-tolerant applications. Depending upon the environment of operation and application sensitivity, the designed processor can be reconfigured to work either in normal mode or fault-tolerant mode. The novelty of the proposed architecture is that the reconfigurable feature reduces the resource overhead and makes the processor energy-efficient by optimally using all four processor cores to provide fault-tolerant results. The proposed computing architecture is designed using Verilog HDL(Hardware Description Language) and synthesized on 32nm CMOS (Complementary Metal-Oxide Semiconductor) process technology node using Synopsys Design Compiler EDA (Electronic Design Automation) tool. Compared to unprotected design, the synthesis tool reports -21.75% reduction in power with a time penalty of +9.96% and area overhead of +17.89% for the proposed fault-tolerant approach. Compared to the state-of-the-art faulttolerant computing system, the proposed design achieves -2.26% low area overhead with its reliability intact as DMR. Further, the proposed processor is prototyped and tested on FPGA (field-programmable gate array) with fault-injection using SEM (soft error mitigation) IP core.INDEX TERMS Reconfigurable VLSI architectures, fault-tolerant processor, FPGA implementation, RISC-V ISA, single event upset.

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Reliability Calculation With Respect to Functional Failures Induced by Radiation in TMR Arm Cortex-M0 Soft-Core Embedded Into SRAM-Based FPGA

Cited by 20 publications

References 16 publications

A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices

A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices

Electromagnetic Occlusion Algorithm Based on FPGA and Panel Grouping and Its Optimization

A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications

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