A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications

Abstract

Radiation can affect the correct behavior of an electronic device. Hence, the microprocessors used for space missions need to be protected against fault. TMR (Triple modular redundancy) is used for mitigating various kinds of faults in an electronic circuit. Although TMR provides an excellent level of reliability, it takes a large area and suffers from high power consumption. To reduce the area and power overheads DMR (double modular redundancy) is used. The DMR approach significantly reduces the resource overhead but it also reduces the performance by imposing timing penalty. Various methods have been proposed since the incarnation of TMR and DMR, but the resource overhead is still a challenging issue. Hence, in this work, a new DMR based reconfigurable quad-core RV32IM processor architecture is proposed for fault-tolerant applications. Depending upon the environment of operation and application sensitivity, the designed processor can be reconfigured to work either in normal mode or fault-tolerant mode. The novelty of the proposed architecture is that the reconfigurable feature reduces the resource overhead and makes the processor energy-efficient by optimally using all four processor cores to provide fault-tolerant results. The proposed computing architecture is designed using Verilog HDL(Hardware Description Language) and synthesized on 32nm CMOS (Complementary Metal-Oxide Semiconductor) process technology node using Synopsys Design Compiler EDA (Electronic Design Automation) tool. Compared to unprotected design, the synthesis tool reports -21.75% reduction in power with a time penalty of +9.96% and area overhead of +17.89% for the proposed fault-tolerant approach. Compared to the state-of-the-art faulttolerant computing system, the proposed design achieves -2.26% low area overhead with its reliability intact as DMR. Further, the proposed processor is prototyped and tested on FPGA (field-programmable gate array) with fault-injection using SEM (soft error mitigation) IP core.INDEX TERMS Reconfigurable VLSI architectures, fault-tolerant processor, FPGA implementation, RISC-V ISA, single event upset.

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

“…Shukla and Ray [41] implement a re-configurable DCLS approach within a quad-core processor based on the RISC-V ISA. The simple, custom-designed core is paired with a mode control unit and a fault detection and correction unit, which ensure proper execution and correction depending on a dedicated mode selection signal.…”

“…Shukla and Ray [41] present a quad-core RISC-V-based processor re-configurable for DCLS operation, introducing up to 17.9% area overhead over the base implementation, while our HMR unit offers more flexibility by introducing just 9% area overhead over a standard 12-cores PULP cluster. In addition, Shukla and Ray rely on saving just the last executed PC for the recovery, which is insufficient to determine the entire state of the grouped cores.…”