Reliability assessment of flipchip on build up laminate based multi-chip package

Chai, Taichong; Lee, C.; Ma, Yiyi; Wong, E.H.; Zhang, X.W.; Pinjala, D.; Murthy, S.; Teo, Poi-Siong

doi:10.1109/ectc.2002.1008181

Cited by 6 publications

(1 citation statement)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The typical failure mode during BLR TC tests is external solder joint cracking and has been reported across different package types (BGA, QFN, Chip on Lead package, WCSP). Extensive work has been done to study this type of failure mode [1][2]. Damage can also occur inside the package and cause BLR failure since Daisy-Chain net goes through die connected to PCB.…”

Section: Introductionmentioning

confidence: 99%

Internal Bump Cracking Risk Assessment for Flip Chip Ball Grid Array Package During Board Level Reliability Test Through Finite Element Analysis

Li,

Gurrum,

Jiang

et al. 2024

IMAPSource Proceedings

View full text Add to dashboard Cite

The performance of semiconductor devices during board-level reliability (BLR) thermal cycling tests continues to be a concern in different applications. The primary focus of those BLR tests is to evaluate the fatigue life of external solder joints between the package and printed circuit board (PCB). For flip-chip ball grid array (FCBGA) package technology, internal solder bumps can also crack and result in open electrical failure. This type of BLR failure has yet to be widely reported in the literature. This article presents failures due to internal solder bump cracks during the BLR test. Failure analysis (FA) clearly shows the cracking location strongly depends on bump density. Finite Element Analysis (FEA) based simulation is performed to understand the failure mechanism. Unlike the standard BLR modeling approach, which focuses on predicting external solder joint fatigue life with correlated data, simulation here has to capture the entire internal bump pattern in the global BLR model. The need to capture the entirety of the bump scheme poses a significant challenge to managing the global model size with a reasonable meshing count and running time. Therefore, a customized post-process approach is developed to analyze bump density impact and enable design optimization.

show abstract

Section: Introductionmentioning

confidence: 99%