Reliability Aspects

Wouters, Dirk J.; Chen, Yangyin; Fantini, A.; Raghavan, Nagarajan

doi:10.1002/9783527680870.ch21

Cited by 5 publications

(6 citation statements)

References 49 publications

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“…10,25,26 The standard deviations normalized to the mean resistance values 0.042 and 0.056, respectively, which are typical values for redox-based memristive devices. 7 In pulsed operation, we obtain similar distributions (Supporting Information, Figure S1). For operation at different current compliances, we obtain an inverse relationship between the LRS resistance value and the current compliance; that is, higher currents lead to lower resistance states (Supporting Information, Figure S1).…”

Section: Resultssupporting

confidence: 65%

“…In the simplest application, the device can be set into a low resistance state (LRS) and reset into a high resistance state (HRS), which may encode a logical one and zero, respectively. The major obstacle delaying large-scale implementation of memristive devices into state-of-the art memory or logic applications, however, is their large cycle-to-cycle (C2C) and device-to-device (D2D) variability of both LRS and HRS resistance values. , These variabilities, which typically follow a log-normal distribution, describe the stochastic nature of the switching process within one cell, resulting in different resistances obtained for each switching cycle and different resistances obtained for different cells on the same chip.…”

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confidence: 99%

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Subfilamentary Networks Cause Cycle-to-Cycle Variability in Memristive Devices

et al. 2017

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A major obstacle for the implementation of redox-based memristive memory or logic technology is the large cycle-to-cycle and device-to-device variability. Here, we use spectromicroscopic photoemission threshold analysis and operando XAS analysis to experimentally investigate the microscopic origin of the variability. We find that some devices exhibit variations in the shape of the conductive filament or in the oxygen vacancy distribution at and around the filament. In other cases, even the location of the active filament changes from one cycle to the next. We propose that both effects originate from the coexistence of multiple (sub)filaments and that the active, current-carrying filament may change from cycle to cycle. These findings account for the observed variability in device performance and represent the scientific basis, rather than prior purely empirical engineering approaches, for developing stable memristive devices.

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Section: Resultssupporting

confidence: 65%

mentioning

confidence: 99%

Subfilamentary Networks Cause Cycle-to-Cycle Variability in Memristive Devices

et al. 2017

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“…of Oxide-Based Resistive Switching Memory scalability, fast operation, low power consumption, and high retention [3], [5]- [9]. Toward the industrial application of ReRAM, its reliability is highly relevant [10]. Along with variability [11] and retention [12], the endurance or maximum number of switching cycles until failure is one of the most important reliability aspects.…”

Section: Impact Of the Ohmic Electrode On The Endurancementioning

confidence: 99%

“…Along with variability [11] and retention [12], the endurance or maximum number of switching cycles until failure is one of the most important reliability aspects. While 10 4 -10 5 cycles are reported as typical endurance for flash memory [10], several groups reported ReRAM devices with an endurance of 10 7 − 10 12 cycles [13]- [18].…”

Section: Impact Of the Ohmic Electrode On The Endurancementioning

confidence: 99%

Impact of the Ohmic Electrode on the Endurance of Oxide-Based Resistive Switching Memory

Wiefels

Witzleben

Huttemann

et al. 2021

IEEE Trans. Electron Devices

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As one of the key aspects in the reliability of redox-based resistive switching memories (ReRAMs), maximizing their endurance is of high relevance for industrial applications. The major limitation regarding endurance is considered the excessive generation of oxygen vacancies during cycling, which eventually leads to irreversible RESET failures. Thus, the endurance could be increased by using combinations of switching oxide and ohmic electrode (OE) metal that provides a high barrier for the generation of oxygen vacancies [defect formation energy (DFE)]. In this work, we present a sophisticated programming algorithm that aims to maximize the endurance within reasonable measurement time. Using this algorithm, we compare ReRAM devices with four different OE metals and confirm the theoretically predicted trend. Thus, our work provides valuable information for device engineering toward higher endurance.

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“…The family of memristor technologies is diverse, and different technologies come with different kinds of device and system non-idealities. These are covered extensively in the available literature, [89] where scalability and reliability issues are discussed in the context of specific memristor technologies. While some of the stringent requirements typically necessary for non-volatile data storage and memory applications might be relaxed for analog and neuromorphic computing, other additional device properties might be specifically required.…”

Section: Some Challenges Of Memristor Technologiesmentioning

confidence: 99%

Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

Mehonić¹,

Sebastian

Rajendran

et al. 2020

Advanced Intelligent Systems

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121

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Three factors are currently driving the main developments in artificial intelligence (AI): availability of vast amounts of data, continuous growth in computing power, and algorithmic innovations. Graphics processing units (GPUs) have been demonstrated as effective co-processors for the implementation of machine learning (ML) algorithms based on deep learning (DL). Solutions based on DL and GPU implementations have led to massive improvements in many AI tasks, but have also caused an exponential increase in demand for computing power. Recent analyses show that the demand for computing power has increased by a factor of 300 000 since 2012, and the estimate is that this demand will double every 3.4 months-at a much faster rate than improvements made historically through Moore's scaling (a sevenfold improvement over the same period of time). [1] At the same time, Moore's law has been slowing down significantly for the last few years, [2] as there are strong indications that we will not be able to continue scaling down complementary metal-oxide-semiconductor (CMOS) transistors. This calls for the exploration of alternative technology roadmaps for the development of scalable and efficient AI solutions. Transistor scaling is not the only way to improve computing performance. Architectural innovations, such as GPUs, field-programmable arrays (FPGAs), and application-specific integrated circuits (ASICs), have all significantly advanced the ML field. [3] A common aspect of modern computing architectures for ML is a move away from the classical von-Neumann architecture that physically separates memory and computing. This approach yields a performance bottleneck that is often the main reason for both energy and speed inefficiency of ML implementations on conventional hardware platforms due to

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Reliability Aspects

Cited by 5 publications

References 49 publications

Subfilamentary Networks Cause Cycle-to-Cycle Variability in Memristive Devices

Subfilamentary Networks Cause Cycle-to-Cycle Variability in Memristive Devices

Impact of the Ohmic Electrode on the Endurance of Oxide-Based Resistive Switching Memory

Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

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