Reliability Analysis of P<sup>+</sup> Pickup on Anti-ESD Performance in Four CMOS Low-Voltage Technology Nodes

Chen, Shen-Li; Lee, Min-Hua

doi:10.1080/03772063.2016.1164634

Cited by 2 publications

(4 citation statements)

References 7 publications

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“…At the same time, with the increase of the number of TLP actions, the promotion of avalanche breakdown became more obvious, and eventually led to the destructive failure of the device. According to engineering experience, for ESDsensitive NMOS devices subjected to damage, if the threshold voltage exceeds 20% of the original value, the device can be judged to have destructive failure [4]. Combining the Table 1, it can be seen that the device has failed after three TLP actions.…”

Section: 1esd Destructive Failure Simulation Resultsmentioning

confidence: 99%

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Simulation of deep submicron MOSFET failure characteristics under ESD stress

Luo

Liu

et al. 2023

International Conference on Optoelectronic Information and Functional Materials (OIFM 2023)

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With the improvement of semiconductor, MOSFET devices are becoming smaller, making devices more sensitive to ESD. Therefore, the ESD research of MOSFET devices becomes more important. Simulation research can reduce the huge cost caused by the test, which plays an important role in ESD protection design. Based on Electrostatic Discharge (ESD) failure mechanism of MOSFET, the destructive and potential failure mechanism of deep submicron NMOSFET under Transmission Line Pulse (TLP) stress are simulated in this paper. The simulation analysis shows that the destructive failure of the device is caused by the breakdown of the oxide layer between the gate and drain due to the very strong electric field triggered by ESD action. Moreover, even if ESD is lower than the failure voltage threshold, multiple actions can also cause device failure. At the same time, the simulation shows that the abnormal charge state of the oxide layer caused by hot carrier injection is an important reason for the potential failure of the device, and the cumulative effect of ESD on the threshold voltage of the device is huge. The simulation study provides a reference for the future application of TLP test technology in simulation research.

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Section: 1esd Destructive Failure Simulation Resultsmentioning

confidence: 99%

“…Notermans Guido et al [3] applied ESD to GGNMOSFET devices and from the analysis of the output current waveform they concluded that the TLP current parameters could be adjusted to achieve the effect of simulating the HBM and MM models. TLP is becoming one of the most effective test methods for ESD protection structure testing [4].…”

Section: Introductionmentioning

confidence: 99%

Simulation of deep submicron MOSFET failure characteristics under ESD stress

Luo

Liu

et al. 2023

International Conference on Optoelectronic Information and Functional Materials (OIFM 2023)

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“…Furthermore, LDMOS devices may act as HV devices and ESD protection device simultaneously. To reduce the effects of ESD, improving the self-protection performance of HV devices is significant [17][18][19][20][21][22][23][24][25][26][27][28]. Therefore, to achieve good ESD capability in devices, parameters including trigger voltage (V t1 ), holding voltage (V h ), and secondary breakdown current (I t2 ) are critical.…”

Section: Introductionmentioning

confidence: 99%

“…Eventually, the ESD immunity of this protection device becomes not proportional to the device size. As shown the voltage-current characteristic curve of a protection device in Figure3, the difference between the secondary breakdown voltage (V t2 ) and V t1 values affects the turned-on probability and non-uniform turned-on issues on each MOSFET[24]. In order to enhance uniform conduction, it is generally desirable to adjust the snapback curve as shown by the dashed curve in Figure3.…”

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confidence: 99%

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

et al. 2020

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An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.

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Reliability Analysis of P⁺ Pickup on Anti-ESD Performance in Four CMOS Low-Voltage Technology Nodes

Cited by 2 publications

References 7 publications

Simulation of deep submicron MOSFET failure characteristics under ESD stress

Simulation of deep submicron MOSFET failure characteristics under ESD stress

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

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Reliability Analysis of P+ Pickup on Anti-ESD Performance in Four CMOS Low-Voltage Technology Nodes

Cited by 2 publications

References 7 publications

Simulation of deep submicron MOSFET failure characteristics under ESD stress

Simulation of deep submicron MOSFET failure characteristics under ESD stress

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

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Reliability Analysis of P⁺ Pickup on Anti-ESD Performance in Four CMOS Low-Voltage Technology Nodes