Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

Abstract

An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.

CMOS Interface Circuits for High-Voltage Automotive Signals

“…The direct sizing of an ESD protection for a breakdown voltage higher than the peak value of the ignition coil or injector signals is not feasible. Indeed, considering a GGNMOS as a clamp device, its drain-to-substrate breakdown voltage must be higher than 400 V. This device is seldom available in high-voltage CMOS technologies with DMOS transistors with a typical breakdown voltage within 100 V [37]. Additionally, a high breakdown voltage could be obtained by stacking several GGNMOS devices [38,39], but with a significant silicon area penalty.…”

“…Therefore, the snap-back voltage of the DMOS transistor must be well above that of the ESD GCNMOS clamp. The plot in Figure 5 shows the measured transmission line pulse (TLP) characteristics [37,41,42] of the ESD clamp and of the 70 V DMOS device. The relatively large range between the trigger voltages V T-MOS and V T-ESD is suitable to allocate the tolerance due to process corner and temperature, affecting both V T-MOS and V T-ESD .…”

Influence of Modifications Related to Safe Operating Area Demands on Operation of a Specialized Medium/High-Voltage Unity-Gain Buffer

“…The layouts of these ESD devices differ discernibly. The pad ESD structures are the most critical and are laid out completely in accordance with the special ESD-optimized process rules [24,25] based on or similar to various published ESD-focused layout optimization methods for MOS transistors [26][27][28] and other devices [27,29]. The local mini structures follow the most critical of these rules.…”

ESD Design and Analysis by Drain Electrode-Embedded Horizontal Schottky Elements for HV nLDMOSs

“…Even a small defect during manufacturing can cause considerable losses to the manufacturer. Electrostatic discharge (ESD) events [1][2][3][4][5][6][7][8][9][10] for integrated circuits (ICs) are the major hazard to reliability.…”