Regrowth-Free GaN-Based Complementary Logic on a Si Substrate

Chowdhury, Nadim; Xie, Qingyun; Yuan, Mengyang; Cheng, Kai; Then, Han Wui; Palacios, Tomás

doi:10.1109/led.2020.2987003

Cited by 86 publications

(48 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A various epitaxial structures of p-type GaN FETs have been demonstrated [110][111][112][113][114][115][116][117]. A GaN complementary inverter circuit comprising of both E-mode n-type GaN FET and p-type GaN FET monolithically integrated on Si Substrate without regrowth technology was also demonstrated [118]. The probe station with thermal chuck were used to characterize the fabricated inverter under high operation temperature.…”

Section: Gan-based Cmos Technologymentioning

confidence: 99%

“…A very high density of 2D hole gas (2DHG) induced by the polarization at the interface of GaN/AlN was discovered [119] which led to the development of p-channel heterostructure field effect transistors (HFETs) that reach the linear current density of 100 mA/mm [112]. A p-channel MISFET with a recessed-gate was grown by metalorganic chemical vapor deposition (MOCVD) using p-GaN/AlGaN/GaN hetrostructure on Si substrate [113,118]. The fabricated structure contains both 2-dimensional electron gas (2DEG) and 2-dimensional hole gas (2DHG) without regrowth technology which is suitable for implementing GaN-based complementary circuit.…”

Section: Gan-based Cmos Technologymentioning

confidence: 99%

See 1 more Smart Citation

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Hsu

Lai

et al. 2021

Micromachines

View full text Add to dashboard Cite

GaN HEMT has attracted a lot of attention in recent years owing to its wide applications from the high-frequency power amplifier to the high voltage devices used in power electronic systems. Development of GaN HEMT on Si-based substrate is currently the main focus of the industry to reduce the cost as well as to integrate GaN with Si-based components. However, the direct growth of GaN on Si has the challenge of high defect density that compromises the performance, reliability, and yield. Defects are typically nucleated at the GaN/Si heterointerface due to both lattice and thermal mismatches between GaN and Si. In this article, we will review the current status of GaN on Si in terms of epitaxy and device performances in high frequency and high-power applications. Recently, different substrate structures including silicon-on-insulator (SOI) and engineered poly-AlN (QST®) are introduced to enhance the epitaxy quality by reducing the mismatches. We will discuss the development and potential benefit of these novel substrates. Moreover, SOI may provide a path to enable the integration of GaN with Si CMOS. Finally, the recent development of 3D hetero-integration technology to combine GaN technology and CMOS is also illustrated.

show abstract

Section: Gan-based Cmos Technologymentioning

confidence: 99%

Section: Gan-based Cmos Technologymentioning

confidence: 99%

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Hsu

Lai

et al. 2021

Micromachines

View full text Add to dashboard Cite

show abstract

“…P. Cui et al demonstrated an 80-nm-gate-length InAlN/GaN HEMT on Si with a record high on/off current (Ion/Ioff) ratio of 1.58 × 10 6 , a steep subthreshold swing (SS) of 65 mV/dec, and a fT of 200 GHz, resulting in a record high fT × Lg = 16 GHz•µm [7]. N. Chowdhury et al demonstrated a complementary logic circuit (an inverter) on a GaN-on-Si platform with a record maximum voltage gain of 27 V/V at an input voltage of 0.59 V with VDD = 5 V [8]. H. Xie et al reported an InAlN/GaN HEMT on Si with a fT of 210 GHz and a three-terminal off-state breakdown voltage (BVds) of 46 V, leading to a record high Johnson's figure-of-merit (JFOM = fT × BVds) of 8.8 THz•V [9].…”

Section: Introductionmentioning

confidence: 99%

Scaling Behavior of InAlN/GaN HEMTs on Silicon for RF Applications

Cui

Zeng

2022

Preprint

View full text Add to dashboard Cite

Due to the low cost and the scaling capability of Si substrate, InAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions. In this paper, a high-performance 50-nm-gate-length InAlN/GaN HEMT on Si with a high on/off current (Ion/Ioff) ratio of 7.28 × 106, an average subthreshold swing (SS) of 72 mV/dec, a low drain-induced barrier lowing (DIBL) of 88 mV, an off-state three-terminal breakdown voltage (BVds) of 36 V, a current/power gain cutoff frequency (fT/fmax) of 140/215 GHz, and a Johnson’s figure-of-merit (JFOM) of 5.04 THz∙V is simultaneously demonstrated. The device extrinsic and intrinsic parameters are extracted using equivalent circuit model, which is verified by the good agreement between simulated and measured S-parameter values. Then the scaling behavior of InAlN/GaN HEMTs on Si is predicted using the extracted extrinsic and intrinsic parameters of devices with different gate lengths (Lg). It presents that a fT/fmax of 230/327 GHz can be achieved when Lg scales down to 20 nm with the technology developed in the study, and an improved fT/fmax of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMT with regrown ohmic contact technology and 30% decreased parasitic capacitance. This study confirms the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.

show abstract

“…Recently, there has been a number of demonstrations of GaN CMOS inverter [11][12][13][14][15][16]. However, all of these demonstrations rely on the integration of lateral AlGaN/GaN high-electron-mobility transistors (HEMTs) and the importance of the scaling theory is not well proven.…”

Section: Introductionmentioning

confidence: 99%

GaN-Based GAA Vertical CMOS Inverter

Liu

Yang

et al. 2022

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

In this work, we simulate the static and dynamic characteristics of gallium nitride (GaN)-based gate-all-around (GAA) vertical nanowire complementary metal-oxide-semiconductor (CMOS) inverter. Based on the 3-D simulator of Silvaco-TCAD, the simulated physical models and associated model parameters have been well calibrated with the reported experimental results of GaN n-channel NWFET and the simulated typical electrical parameters match the measured data. According to the simulation results, the GaN GAA vertical nanowire CMOS inverter exhibits rail-to-rail operation, low static power dissipation, large noise margins, high thermal stability and good scalability.

show abstract

Regrowth-Free GaN-Based Complementary Logic on a Si Substrate

Cited by 86 publications

References 18 publications

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Scaling Behavior of InAlN/GaN HEMTs on Silicon for RF Applications

GaN-Based GAA Vertical CMOS Inverter

Contact Info

Product

Resources

About