Region-based hierarchical operation partitioning for multicluster processors

Abstract

Clustered architectures are a solution to the bottleneck of centralized register files in superscalar and VLIW processors. The main challenge associated with clustered architectures is compiler support to effectively partition operations across the available resources on each cluster. In this work, we present a novel technique for clustering operations based on graph partitioning methods. Our approach incorporates new methods of assigning weights to nodes and edges within the dataflow graph to guide the partitioner. Nodes are assigned weights to reflect their resource usage within a cluster, while a slack distribution method intelligently assigns weights to edges to reflect the cost of inserting moves across clusters. A multilevel graph partitioning algorithm, which globally divides a dataflow graph into multiple parts in a hierarchical manner, uses these weights to efficiently generate estimates for the quality of partitions. We found that our algorithm was able to achieve an average of 20% improvement in DSP kernels and 5% improvement in SPECint2000 for a four-cluster architecture.

A software-hardware hybrid steering mechanism for clustered microarchitectures

“…One important category is the code generation for loops [1,2,10,20,25] by means of modulo scheduling techniques [9,23]. Another category schedules instructions for more general program structures including cyclic and acyclic control flow graphs [6,8,12,13,16,17,21]. In this paper, we focus on the latter category.…”

“…VLIW) [6,13,8,12,16,17,21], where the compiler is responsible for both code scheduling and instruction distribution among clusters. However, as we will show later in this paper, the softwareonly approach performs much worse than its hardware-only counterpart when it is applied to out-of-order processors.…”

PALF: compiler supports for irregular register files in clustered VLIW DSP processors

“…Codina et al [24] used a similar strategy as UAS but focused on modulo scheduling. Using graph partitioners for clustering operations has also been investigated in several studies [5,25]. Most of these studies were much different from our work, since our architecture has more features than clustering, and we mainly focus on register allocation targeted toward acyclic code to tie in with the phase ordering in ORC infrastructure.…”

Partitioning Multi-Threaded Processors with a Large Number of Threads

“…The only drawback of such an architecture is the intercluster communication cost. Various groups [2,3,4,6,9,10] have studied cluster assignment mechanisms for one thread to reduce the overhead of inter-cluster communication. We extend their ideas to a clustered architecture with multiple threads.…”