Partitioning Multi-Threaded Processors with a Large Number of Threads

El-Moursy, Ali A.; Garg, Rajeev; Albonesi, David H.; Dwarkadas, Sandhya

doi:10.1109/ispass.2005.1430566

Cited by 20 publications

(15 citation statements)

References 37 publications

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“…Similar results were published by Moon [9], who discovered, that static partitioning and execution in-order has only little negative effect on the performance while significantly reducing design complexity. Other studies that divide the pipeline into an out-of-order front-end and an in-order back-end [10] or that restrict certain parts of the pipeline to in-order execution [11] approved the advantages of in-order execution.…”

Section: Related Workmentioning

confidence: 99%

How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT

Mische

Guliashvili

Uhrig

et al. 2010

Architecture of Computing Systems - ARCS 2010

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Abstract. This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-time applications. For superscalar in-order architectures the calculation of the Worst Case Execution Time (WCET) is much easier and tighter than for out-of-order architectures. By a careful enhancement that completely isolates the threads, this capability can be perpetuated to an in-order SMT architecture. Our design goal is to minimise the WCET of the highest priority thread, while releasing as many resources as possible for the execution of concurrent non critical threads. The resultant processor executes hard real-time threads at the same speed as its singlethreaded ancestor, but idle issue slots are dynamically used by non critical threads. The modifications to enable SMT include a multithreaded fetch stage, an additional real-time issue stage, a wider register set, a prioritised multithreaded memory interface, split phase loads and interruptible microcodes for multi-cycle operations. The application of these enhancements is demonstrated by CarCore, a multithreaded embedded processor that implements the Infineon Tricore instruction set.

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Section: Related Workmentioning

confidence: 99%

How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT

Mische

Guliashvili

Uhrig

et al. 2010

Architecture of Computing Systems - ARCS 2010

View full text Add to dashboard Cite

show abstract

“…The baseline processor is a clustered multithreaded (CMT) machine [13] with a unified frontend, and 16 cores containing functional units, register files, and data caches for a back-end, as shown in Figure 3. The simulator is based on Simplescalar-3.0 [5] for the Alpha AXP instruction set with the Wattch [4] and HotSpot [16] extensions.…”

Section: Architectural Designmentioning

confidence: 99%

“…Using the same classification system as [13], two communication bound workloads and an instruction level parallelism (ILP) bound workload are examined. The mixes are listed in Table 4.…”

Section: Benchmarksmentioning

confidence: 99%

“…Prior research has shown that the communication delays involved with additional cores negate any performance gain from the increase in the number of functional units [13,19]. Program Command Line Arguments FFT -m18 -p8 -n1024 -l6 -t Jacobi -p8 -v -s512 -i10 LU -n512 -p8 -b16 -t Radix -p8 -n131072 -r16 -m524288 -t Figure 7.…”

Section: Benchmarksmentioning

confidence: 99%

“…Thus, it is unclear from a systems perspective whether the use of optical interconnects to replace global on-chip wires is an attractive solution. In this paper, silicon-based optics for on-chip interconnects are investigated for a large-scale Clustered Multi-Threaded (CMT) processor microarchitecture [13]. Projections for optical and electrical interconnects for 45 nm CMOS are presented based on prior work [7,8].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Alleviating Thermal Constraints While Maintaining Performance Via Silicon- Based On-chip Optical Interconnects

Briggs¹,

Chen²,

Nelson³

et al. 2007

Unique Chips and Systems

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The relentless pursuit of Moore's Law by the semiconductor industry has yielded significant increases in performance, but at the cost of greater power dissipation. As CMOS technology continues to scale, increasing power densities, or "hot spots," particularly in dense logic structures, may limit frequencies below projected targets in order to avoid circuit malfunction. A solution to this problem is to separate the hot spots by interleaving these units with cooler cache banks. This approach, however, increases the distance among processing functions, which can significantly degrade performance. While effort is made to localize communication as much as possible, global communication cannot be completely avoided, particularly in parallel applications.In this paper, the use of silicon-based on-chip optical interconnects is investigated for minimizing the performance gap created by separating processing functions due to thermal constraints. Models of optical components are presented, and used to connect the common front-end with the distributed back-ends of a large-scale Clustered MultiThreaded (CMT) processor. A significant reduction in thermal constraints (translated into an increase in clock frequency), combined with improved instructions per cycle (IPC), is demonstrated over a conventional all-electrical system.

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Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors

Hasasneh

Bell

Jesshope

2006

Architecture of Computing Systems - ARCS 2006

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Partitioning Multi-Threaded Processors with a Large Number of Threads

Abstract: Today 's general-purpose

Cited by 20 publications

References 37 publications

How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT

How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT

Alleviating Thermal Constraints While Maintaining Performance Via Silicon- Based On-chip Optical Interconnects

Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors

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