Region-based hierarchical operation partitioning for multicluster processors

Abstract

Clustered architectures are a solution to the bottleneck of centralized register files in superscalar and VLIW processors. The main challenge associated with clustered architectures is compiler support to effectively partition operations across the available resources on each cluster. In this work, we present a novel technique for clustering operations based on graph partitioning methods. Our approach incorporates new methods of assigning weights to nodes and edges within the dataflow graph to guide the partitioner. Nodes are assigned weights to reflect their resource usage within a cluster, while a slack distribution method intelligently assigns weights to edges to reflect the cost of inserting moves across clusters. A multilevel graph partitioning algorithm, which globally divides a dataflow graph into multiple parts in a hierarchical manner, uses these weights to efficiently generate estimates for the quality of partitions. We found that our algorithm was able to achieve an average of 20% improvement in DSP kernels and 5% improvement in SPECint2000 for a four-cluster architecture.

SIMD defragmenter

“…From these two subgraphs, (3,4,6) is chosen to be executed in the unused lanes. As a result, instructions (1,2,5,7) and (3,4,6) are executed in lane 0-3 and 4-7 as shown in Figure 8(b). In addition to this, one cycle of overhead is incurred to move the output data of instruction 6 to lane 0-3.…”

“…This scheme is highly related to the research in the area of clustering [1,6,7,13]. However, general clustering techniques for VLIW machines focus on load balancing and critical path search, and thus cannot handle dataflow and instruction mismatches between clusters.…”

“…Superword level parallelism difficulty: (a)(1,3,5,7) and(2,4,6) are chosen to execute in parallel and three overheads occur, (b) superword level parallelism exploited output source code, and (c) average cycle savings of SLP: Y-bar means ideal savings and it is broken down as overheads and real savings.…”

Compiler supports for VLIW DSP processors with SIMD intrinsics

“…Chu et al . employed region‐based partitioning on weighted data‐flow graph to obtain a best cut. Besides, modulo scheduling with partitioning techniques has also been proposed for clustered architectures.…”

A distributed control path architecture for VLIW processors

“…The first step is to perform operation partitioning to assign operations to clusters [11,6]. We use a typical partitioning algorithm that attempts to maximize performance by balancing the application workload across the clusters while minimizing the number of required ICMOVEs.…”