Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies

Abstract

As manycores use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low voltage, leakage in on-chip memory modules contributes substantially to the chip's power draw. This is unfortunate, given that, intuitively, the large multi-level cache hierarchy of a manycore is likely to contain a lot of useless data.An effective way to reduce this problem is to use a lowleakage technology such as embedded DRAM (eDRAM). However, eDRAM requires refresh. In this paper, we examine the opportunity of minimizing on-chip memory power further by intelligently refreshing on-chip eDRAM. We present Refrint, a simple approach to perform fine-grained, intelligent refresh of on-chip eDRAM multiprocessor cache hierarchies. We introduce the Refrint algorithms and microarchitecture. We evaluate Refrint in a simulated manycore running 16-threaded parallel applications. We show that an eDRAM-based memory hierarchy with Refrint consumes only 30% of the energy of a conventional SRAM-based memory hierarchy, and induces a slowdown of only 6%. In contrast, an eDRAM-based memory hierarchy without Refrint consumes 56% of the energy of the conventional memory hierarchy, inducing a slowdown of 25%.

Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

“…This avoids unnecessary refreshes of lines that were recently accessed. Refrint [1] uses count bits instead of counters to reduce the refresh power in eDRAM-based caches in two ways. First, it avoids refreshing recently-accessed lines.…”

“…EDRAM cells require periodic refresh, which can also consume substantial energy for large caches [1,34]. In reality, it is well known that different eDRAM cells can exhibit very different charge-retention properties and, therefore, have different refresh needs.…”

Extreme-scale computer architecture: Energy efficiency from the ground up

“…However, eDRAM needs to be refreshed. Fortunately, refresh is done at the fine-grained level of a cache line, and we can design intelligent refresh schemes [14], [15].…”

“…The other lines are not refreshed and marked as invalid -after being written back to the next level of the hierarchy if they were dirty. To identify such lines we can dynamically use the history of line accesses [14] or programmer hints.…”

Hybrid caches: design and data management

“…Another recent work [34] delays periodic refreshes taking into account the implicit refresh of regular accesses. In addition, authors propose a refresh policy that makes use of a 5-bit counter per cache line.…”