Refresh pausing in DRAM memory systems

Nair, Prashant J.; Chou, Chiachen; Qureshi, Moinuddin K.

doi:10.1145/2579669

Cited by 27 publications

(6 citation statements)

References 16 publications

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“…We report 2015 instead of 2020 because 2020 shows a regression in CAS latency due to first-generation DDR5 chips, which we believe is not representative because of its immature technology 6. Also referred to as refresh overhead[208] and refresh duty cycle[209].…”

mentioning

confidence: 99%

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today's DRAM technology scaling challenges requires new solutions driven by both DRAM producers and consumers. In this paper, we observe that the separation of concerns between producers and consumers specified by industry-wide DRAM standards is becoming a liability to progress in addressing scaling-related concerns.To understand the problem, we study four key directions for overcoming DRAM scaling challenges using system-memory cooperation: (i) improving memory access latencies; (ii) reducing DRAM refresh overheads; (iii) securely defending against the RowHammer vulnerability; and (iv) addressing worsening memory errors. We find that the single most important barrier to advancement in all four cases is the consumer's lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, we recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, we propose adopting this revision in a two-step plan, starting with immediate information release through crowdsourcing and publication and culminating in widespread modifications to DRAM standards.

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mentioning

confidence: 99%

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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“…We evaluate adaptive row addressing using a detailed memory system simulator USIMM [7], employed in recent memory-system research [30,35,5,8]. We extended USIMM with: 1) the latency of CA transfers; 2) the latency of the RDIMM's register [23]; 3) DDR4 timing constraints; 4) DDR4 power model that implements Micron's DDR4 System Power Calculator [28] and in addition estimates the dynamic power of the CA bus 10 ; 5) the row:rank:bank: block:channel:block offset physical-to-DRAM address mapping (baseline for the open-page row-buffer management policy) [19]; and 6) an address extension that separates the physical address spaces of different programs by adding unique, random bits right after the block field 11 .…”

Section: Methodsmentioning

confidence: 99%

Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories

Knyaginin

Papaefstathiou

Stenström

2016

Proceedings of the Second International Symposium on Memory Systems

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Modern commercial workloads drive a continuous demand for larger and still low-latency main memories. JEDEC member companies indicate that parallel memory protocols will remain key to such memories, though widening the bus (increasing the pin count) to address larger capacities would cause multiple issues ultimately reducing the speed (the peak data rate) and cost-efficiency of the protocols. Thus to stay high-speed and cost-efficient, parallel memory protocols should address larger capacities using the available number of pins. This is accomplished by multiplexing the pins to transfer each address in multiple bus cycles, implementing Multi-Cycle Addressing (MCA). However, additional address-transfer cycles can significantly worsen performance and energy efficiency. This paper contributes with the concept of adaptive row addressing that comprises rowaddress caching to reduce the number of address-transfer cycles, enhanced by row-address prefetching and an adaptive row-access priority policy to improve state-of-the-art memory schedulers. For a case-study MCA protocol, the paper shows that the proposed concept improves: i) the read latency by 7.5% on average and up to 12.5%, and ii) the system-level performance and energy efficiency by 5.5% on average and up to 6.5%. This way, adaptive row addressing makes the MCA protocol as efficient as an idealistic protocol of the same speed but with enough pins to transfer each row address in a single bus cycle.

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“…Nair et al [56] presented a fault simulator tool called FaultSim for evaluating reliability mechanisms' effectiveness in two-dimensional (2D) and three-dimensional (3D) stacked memories. The FaultSim tool can be used to evaluate various ECC and spare mechanisms for memories and TSVs.…”

Section: Simulators For Measuring Reliability and Repair Efficiencymentioning

confidence: 99%

Memory built-in self-repair and correction for improving yield: a review

Sontakke,

Atchina

2024

IJECE

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Nanometer memories are highly prone to defects due to dense structure, necessitating memory built-in self-repair as a must-have feature to improve yield. Today’s system-on-chips contain memories occupying an area as high as 90% of the chip area. Shrinking technology uses stricter design rules for memories, making them more prone to manufacturing defects. Further, using 3D-stacked memories makes the system vulnerable to newer defects such as those coming from through-silicon-vias (TSV) and micro bumps. The increased memory size is also resulting in an increase in soft errors during system operation. Multiple memory repair techniques based on redundancy and correction codes have been presented to recover from such defects and prevent system failures. This paper reviews recently published memory repair methodologies, including various built-in self-repair (BISR) architectures, repair analysis algorithms, in-system repair, and soft repair handling using error correcting codes (ECC). It provides a classification of these techniques based on method and usage. Finally, it reviews evaluation methods used to determine the effectiveness of the repair algorithms. The paper aims to present a survey of these methodologies and prepare a platform for developing repair methods for upcoming-generation memories.

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Refresh pausing in DRAM memory systems

Cited by 27 publications

References 16 publications

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories

Memory built-in self-repair and correction for improving yield: a review

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