Refresh Now and Then

Baek, Seungjae; Cho, Sangyeun; Melhem, Rami

doi:10.1109/tc.2013.164

Cited by 50 publications

(59 citation statements)

References 10 publications

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“…We model these errors with two key parameters: 1) P is the percentage of weak cells (i.e., cells that fail with reduced DRAM parameters), and 2) F A is the probability of an error in any weak cell. Such uniform random distributions are already observed in prior works [10,53,133,164]. • Error Model 1: the bit errors follow a vertical distribution across the bitlines of a DRAM bank.…”

Section: Enabling Eden With Error Modelssupporting

confidence: 58%

Eden

Koppula

Orosa

Yağlıkçı

et al. 2019

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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The effectiveness of deep neural networks (DNN) in vision, speech, and language processing has prompted a tremendous demand for energy-efficient high-performance DNN inference systems. Due to the increasing memory intensity of most DNN workloads, main memory can dominate the system's energy consumption and stall time. One effective way to reduce the energy consumption and increase the performance of DNN inference systems is by using approximate memory, which operates with reduced supply voltage and reduced access latency parameters that violate standard specifications. Using approximate memory reduces reliability, leading to higher bit error rates. Fortunately, neural networks have an intrinsic capacity to tolerate increased bit errors. This can enable energy-efficient and high-performance neural network inference using approximate DRAM devices.Based on this observation, we propose EDEN, the first general framework that reduces DNN energy consumption and DNN evaluation latency by using approximate DRAM devices, while strictly meeting a user-specified target DNN accuracy. EDEN relies on two key ideas: 1) retraining the DNN for a target approximate DRAM device to increase the DNN's error tolerance, and 2) efficient mapping of the error tolerance of each individual DNN data type to a corresponding approximate DRAM partition in a way that meets the user-specified DNN accuracy requirements.We evaluate EDEN on multi-core CPUs, GPUs, and DNN accelerators with error models obtained from real approximate DRAM devices. We show that EDEN's DNN retraining technique reliably improves the error resiliency of the DNN by an order of magnitude. For a target accuracy within 1% of the original DNN, our results show that EDEN enables 1) an average DRAM energy reduction of 21%, 37%, 31%, and 32% in CPU, GPU, and two different DNN accelerator architectures, respectively, across a variety of state-ofthe-art networks, and 2) an average (maximum) speedup of 8% (17%) and 2.7% (5.5%) in CPU and GPU architectures, respectively, when evaluating latency-bound neural networks.

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Section: Enabling Eden With Error Modelssupporting

confidence: 58%

Eden

Koppula

Orosa

Yağlıkçı

et al. 2019

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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show abstract

“…For example, several previous studies have proposed fine-grained methods to control DRAM parameters based on the retention time measured for each cell [40], [62]. To measure the retention time, authors use micro-benchmarks that implement the worst-case data pattern manifesting errors in the vast majority of error-prone memory locations [3], [19], [22], [27]. However, our study shows that real applications may trigger errors in many more memory locations than the conventional data pattern microbenchmarks.…”

Section: Dram Error Behavior: Workload-dependent Parametersmentioning

confidence: 99%

“…Many studies have proposed to model DRAM errors for investigation either hardware design efficiency [41] or software fault tolerance [36], [37], [42], [43]. However, all those studies use constant DRAM error rates extracted on real DRAMs when running the data pattern micro-benchmarks [3], [19], [22], [40], [62]. Our model can be used to improve those studies and proposed techniques by considering workload-aware DRAM error behavior.…”

Section: Workload-aware Modeling Vs Conventional Modelingmentioning

confidence: 99%

Workload-Aware DRAM Error Prediction using Machine Learning

Mukhanov

Tovletoglou

Vandierendonck

et al. 2019

2019 IEEE International Symposium on Workload Characterization (IISWC)

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The aggressive scaling of technology may have helped to meet the growing demand for higher memory capacity and density, but has also made DRAM cells more prone to errors. Such a reality triggered a lot of interest in modeling DRAM behavior for either predicting the errors in advance or for adjusting DRAM circuit parameters to achieve a better tradeoff between energy efficiency and reliability. Existing modeling efforts may have studied the impact of few operating parameters and temperature on DRAM reliability using custom FPGAs setups, however they neglected the combined effect of workloadspecific features that can be systematically investigated only on a real system.In this paper, we present the results of our study on workloaddependent DRAM error behavior within a real server considering various operating parameters, such as the refresh rate, voltage and temperature. We show that the rate of single-and multi-bit errors may vary across workloads by 8x, indicating that program inherent features can affect DRAM reliability significantly. Based on this observation, we extract 249 features, such as the memory access rate, the rate of cache misses, the memory reuse time and data entropy, from various compute-intensive, caching and analytics benchmarks. We apply several supervised learning methods to construct the DRAM error behavior model for 72 servergrade DRAM chips using the memory operating parameters and extracted program inherent features. Our results show that, with an appropriate choice of program features and supervised learning method, the rate of single-and multi-bit errors can be predicted for a specific DRAM module with an average error of less than 10.5 %, as opposed to the 2.9x estimation error obtained for a conventional workload-unaware error model. Our model enables designers to predict DRAM errors in advance for less than a second and study the impact of any workload and applied software optimizations on DRAM reliability.

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“…There are several works on retention aware refresh, that also try to reduce the number of refresh events but unlike approximate DRAM they assure full data integrity [33,22,2,20,36,34]. These techniques can be applied in fields of non-resilient applications.…”

Section: B Retention Aware Refreshmentioning

confidence: 99%

Efficient reliability management in SoCs - an approximate DRAM perspective

Jung

Mathew

Weis

et al. 2016

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

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In today's computing systems Dynamic Random Access Memories (DRAMs) have a large influence on performance and contribute significantly to the total power consumption. Thus, recent research activities bring the idea of approximate DRAM into focus to save power and improve performance by lowering the refresh rate or disabling refresh completely. Hence, fast and accurate models are required for a thoroughly exploration of approximate DRAM for error resilient applications. In this paper we present a holistic simulation environment for investigations on approximate DRAM and show the impact on error resilient applications.

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Refresh Now and Then

Cited by 50 publications

References 10 publications

Eden

Eden

Workload-Aware DRAM Error Prediction using Machine Learning

Efficient reliability management in SoCs - an approximate DRAM perspective

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