Reexecution and Selective Reuse in Checkpoint Processors

Golander, Amit; Weiss, Shlomo

doi:10.1007/978-3-642-00904-4_13

Cited by 4 publications

(5 citation statements)

References 35 publications

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“…We used SimpleScalar [Burger and Austin 1997] for performance simulation. We modified its sim-outorder model to implement checkpoints; variable length pipelines; variable size register files; instruction queues (IQ); a stateof-the-art branch predictor (TAGE [Seznec and Michaud 2006]); a mechanism that completely hides the rollback penalty, regardless of the state of the pipeline (CRB [Golander and Weiss 2008]); and a method to reuse the outcome of branches, achieving near-perfect prediction during re-execution (RbckBr [Golander and Weiss 2007]). The simulation parameters of the baseline microarchitecture (refer to Table I) mostly follow the parameters of Power5 [Kalla et al 2004].…”

Section: Experimental Methodologymentioning

confidence: 99%

Checkpoint allocation and release

Golander

Weiss

2009

ACM Trans. Archit. Code Optim.

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Out-of-order speculative processors need a bookkeeping method to recover from incorrect speculation. In recent years, several microarchitectures that employ checkpoints have been proposed, either extending the reorder buffer or entirely replacing it. This work presents an in-dept-study of checkpointing in checkpoint-based microarchitectures, from the desired content of a checkpoint, via implementation trade-offs, and to checkpoint allocation and release policies. A major contribution of the article is a novel adaptive checkpoint allocation policy that outperforms known policies. The adaptive policy controls checkpoint allocation according to dynamic events, such as second-level cache misses and rollback history. It achieves 6.8% and 2.2% speedup for the integer and floating point benchmarks, respectively, and does not require a branch confidence estimator. The results show that the proposed adaptive policy achieves most of the potential of an oracle policy whose performance improvement is 9.8% and 3.9% for the integer and floating point benchmarks, respectively. We exploit known techniques for saving leakage power by adapting and applying them to checkpoint-based microarchitectures. The proposed applications combine to reduce the leakage power of the register file to about one half of its original value.

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Section: Experimental Methodologymentioning

confidence: 99%

Checkpoint allocation and release

Golander

Weiss

2009

ACM Trans. Archit. Code Optim.

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“…Hardware approaches have been used to reuse results of long-latency alu operations [7,8,9,10,11] and compress functions or arbitrary sequences of instructions into a single memoized result [12,7,8,13,14,15,16,17,18]. Further studies were performed to analyze the effectiveness and propose solutions for instruction reuse in the hardware [19,20,21,22,23,24,25,26,27].…”

Section: Related Workmentioning

confidence: 99%

Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors

Long

Franklin

Biswas

et al. 2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

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-Parallelism is the key to continued performance scaling in modern microprocessors. Yet we observe that this parallelism can often contain a surprising amount of instruction redundancy. We propose to exploit this redundancy to improve performance and decrease energy consumption.We propose a multi-threading micro-architecture, Minimal Multi-Threading (MMT), that leverages register renaming and the instruction window to combine the fetch and execution of identical instructions between threads in SPMD applications. While many techniques exploit intra-thread similarities by detecting when a later instruction may use an earlier result, MMT exploits inter-thread similarities by, whenever possible, fetching instructions from different threads together and only splitting them if the computation is unique. With two threads, our design achieves a speedup of 1.15 (geometric mean) over a twothread traditional SMT with a trace cache. With four threads, our design achieves a speedup of 1.25 (geometric mean) over a traditional SMT processor with four-threads and a trace cache. These correspond to speedups of 1.5 and 1.84 over a traditional out-of-order processor. Moreover, our performance increases in most applications with no power increase because the increase in overhead is countered with a decrease in cache accesses, leading to a decrease in energy consumption for all applications.

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“…The memo table is accessed in parallel with the first computation cycle, and the computation halts in the case of hit. Thus, memoing reduces a multi-cycle operation to one-cycle when there is a hit in the memo Golander and Weiss present in [Gol07] different instruction reuse methods for Checkpoint Processors. In checkpoint microarchitectures a misspeculation initiates the rollback, in which the latest safe checkpoint preceding the point of misprediction is recovered, and the reexecution of the entire code segment between the recovered checkpoint and the mispredicting instruction (selective reissue).…”

Section: Related Workmentioning

confidence: 99%

“…We considered the following operations: V*0, V*1, 0/V, V/1 and V/V. A simple hardware scheme for detecting trivial computations and selecting the result is presented in [Gol07] and consists in comparators for the input operands and selectors for the write-back. If during the dispatch stage, a MUL instruction is detected with an operand value of 0 or 1, the result is provided by the detector, avoiding the functional unit allocation and execution.…”

Section: Selective Dynamic Instruction Reusementioning

confidence: 99%

Exploiting selective instruction reuse and value prediction in a superscalar architecture

Gellért

Florea

Vintan

2009

Journal of Systems Architecture

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Abstract:In our previously published research we discovered some very difficult to predict branches, called unbiased branches. Since the overall performance of modern processors is seriously affected by misprediction recovery, especially these difficult branches represent a source of important performance penalties. Our statistics show that about 28% of branches are dependent on critical Load instructions. Moreover, 5.61% of branches are unbiased and depend on critical Loads, too. In the same way, about 21% of branches depend on MUL/DIV instructions whereas 3.76% are unbiased and depend on MUL/DIV instructions. These dependences involve high-penalty mispredictions becoming serious performance obstacles and causing significant performance degradation in executing instructions from wrong paths. Therefore, the negative impact of (unbiased) branches over global performance should be seriously attenuated by anticipating the results of long-latency instructions, including critical Loads. On the other hand, hiding instructions' long latencies in a pipelined superscalar processor represents an important challenge itself. We developed a superscalar architecture that selectively anticipates the values produced by high-latency instructions. In this work we are focusing on Multiply, Division and Loads with miss in L1 data cache, implementing a Dynamic Instruction Reuse scheme for the MUL/DIV instructions and a simple Last Value Predictor for the critical Load instructions. Our improved superscalar architecture achieves an average IPC speedup of 3.5% on the integer SPEC 2000 benchmarks, of 23.6% on the floating-point benchmarks, and an improvement in energy-delay product (EDP) of 6.2% and 34.5%, respectively. We also quantified the impact of our developed Selective Instruction Reuse and Value Prediction techniques in a simultaneous multithreaded architecture (SMT) that implies per thread Reuse Buffers and Load Value Prediction Tables. Our simulation results showed that the best improvements on the SPEC integer applications have been obtained with 2 threads: an IPC speedup of 5.95% and an EDP gain of 10.44%. Although, on the SPEC floating-point programs, we obtained the highest improvements with the enhanced superscalar architecture, the SMT with 3 threads also provides an important IPC speedup of 16.51% and an EDP gain of 25.94%.

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Reexecution and Selective Reuse in Checkpoint Processors

Cited by 4 publications

References 35 publications

Checkpoint allocation and release

Checkpoint allocation and release

Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors

Exploiting selective instruction reuse and value prediction in a superscalar architecture

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