Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors

Abstract

-Parallelism is the key to continued performance scaling in modern microprocessors. Yet we observe that this parallelism can often contain a surprising amount of instruction redundancy. We propose to exploit this redundancy to improve performance and decrease energy consumption.We propose a multi-threading micro-architecture, Minimal Multi-Threading (MMT), that leverages register renaming and the instruction window to combine the fetch and execution of identical instructions between threads in SPMD applications. While many techniques exploit intra-thread similarities by detecting when a later instruction may use an earlier result, MMT exploits inter-thread similarities by, whenever possible, fetching instructions from different threads together and only splitting them if the computation is unique. With two threads, our design achieves a speedup of 1.15 (geometric mean) over a twothread traditional SMT with a trace cache. With four threads, our design achieves a speedup of 1.25 (geometric mean) over a traditional SMT processor with four-threads and a trace cache. These correspond to speedups of 1.5 and 1.84 over a traditional out-of-order processor. Moreover, our performance increases in most applications with no power increase because the increase in overhead is countered with a decrease in cache accesses, leading to a decrease in energy consumption for all applications.

Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP

“…3) Instruction redundancy in SMT: Minimal Multi-threading or MMT favors thread synchronization in the front-end of an SMT core to combine the instruction fetch and decode, and avoid redundant computation between threads [27]. Instructions that operate on different data are broken back into independent scalar instructions executed independently in a conventional out-of-order engine.…”

Simultaneous branch and warp interweaving for sustained GPU performance

“…Minimal Multi Threading shares identical instructions across threads in an out-of-order SMT architecture [23]. Control-flow reconvergence is detected by comparing the PC histories of threads.…”

“…In addition to sharing instructions, recent works also factor out common computations or common data across threads [4,5,9,23]. We expect that SBI and SWI can be combined with data-sharing techniques to improve their flexibility in the face of data divergence.…”

A Hardware and Software Integrated Approach for Adaptive Thread Management in Multicore Multithreaded Microprocessors

“…Long et al [31] proposed to detect the Single Program Multiple Data (SPMD) portion in the benchmark, such that it requires only one instruction fetch for different threads. If the identical instructions required the same input, the execution was limited to one time while the results were duplicated to different threads.…”

“…Moreover, reducing the communication time within parallel programmes was convenient for performance improvement, especially when compilers were employed for a priori knowledge, e.g., [41,31,40]. However, possible contribution from the instruction fetch policy was underestimated, and the mutual impacts among different programmes, similar to the inter-thread interference for multi-programming workloads, were not addressed well.…”