2013 21st Signal Processing and Communications Applications Conference (SIU) 2013
DOI: 10.1109/siu.2013.6531372
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Reed-solomon decoder hardware implementation for DVB-S receiver

Abstract: Özetçe -Bu bildiride, sayısal video uydu yayını standartları kapsamında belirlenmiş olan kısaltılmış Reed-Solomon (n=204, k=108) kod çözme algoritmasının Maple ve MATLAB programları yardımı ile benzetimleri yapılmıştır. Daha sonra bu algoritmanın FPGA üzerinde VHDL kullanarak hızlı, esnek ve üretimi kolay bir tasarımı modellenmiş ve gerçeklenmiştir. Tasarımda hız faktörü, esneklik ve fabrikasyon göz önüne alınarak, algoritmada en çok kullanılan aritmetik işlem olan sonlu alan çarpıcısı için hücresel dizi çarpm… Show more

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Cited by 1 publication
(1 citation statement)
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“…As a first approach, implementations of computational intense decoding blocks was analyzed independently, such as convolutional decoding implementations [13] and the inversion of the Reed-Solomon code [14]. In these and other comparable papers, an implementation of these system parts in hardware-based form, for example in the form of an ASIC or FPGA, is very often proposed.…”
Section: Related Workmentioning
confidence: 99%
“…As a first approach, implementations of computational intense decoding blocks was analyzed independently, such as convolutional decoding implementations [13] and the inversion of the Reed-Solomon code [14]. In these and other comparable papers, an implementation of these system parts in hardware-based form, for example in the form of an ASIC or FPGA, is very often proposed.…”
Section: Related Workmentioning
confidence: 99%