Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration

Identifying sequential redundancies without search

“…The results of [4] [5] [6] [7] [11] are for redundancy removal, those of [5] [6] [12] [13] are based on incorrect theoretical results, those of [7] are not relevant for the original benchmark circuits without a global reset, those of [8] [9] are only for untestability, those of [16] deal with a restricted definition of redundancy, those of [21] are for sequential optimization and include only the smaller benchmark circuits, and those of [10] and [11] do not deal with benchmark circuits. A deterministic sequential test generator performing exhaustive search can identify all faults found by FIRES as untestable, if given enough time.…”

“…Unlike [7] , FIRES can be used for circuits without a global reset. FIRES is a direct method to identify redundancies and can be used efficiently in synthesis to remove sequential redundancies.…”

“…Sequential RID based on implicit state enumeration was proposed in [7] . This method uses ATG and relies on the simplifying assumption that the circuit has a fault-free global reset.…”

“…Most of the previous work on the identification of sequentially untestable and redundant faults [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] is based on ATG. Cheng proposed a procedure for identifying and removing a subset of sequential redundancies (called feedback-free sequential redundancies) [4] [5] [6] .…”

Advanced techniques for GA-based sequential ATPGs

“…The symbolic approach [CHSo93] exploits techniques for Boolean function representation and manipulation which were initially developed for formal verification; this approach is based on a complete algorithm, too, and is very effective when small-and medium-sized circuits are considered. Unfortunately, it is completely unapplicable when circuits with more than some tens of Flip-Flops are dealt with.…”